LG LAC6700R, Руководство по обслуживанию

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2-16
Pin Name in Micom Name in Model Enable I/O I/O setted Output Format Description
51 AVSS
52 P157/ANI15 PKEY1 I/O I - Key #1 line input
53 P156/ANI14 PKEY2 I/O I - Key #2 line input
54 P155/ANI13 PLEVEL_METER I/O I - Level meter input
55 P154/ANI12 PSMETER I/O I - Radio station's strength signal input
56 P153/ANI11 PQUALTY I/O I - Connect to tuner pack QUALITY
57 P152/ANI10 PEJECT I/O I - Eject key input
58 P151/ANI9 PDIM_OUT I/O O CMOS Dimmer output
59 P150/ANI8 PLIGHT I/O O CMOS Backlight control output
60 P27/ANI7 PAUX_MUTE I/O O CMOS AUX mute
61 P26/ANI6 PAUDIO_MUTE I/O O CMOS VR IC <--> PWR AMP mute
62 P25/ANI5 PTEL_MUTE I/O O CMOS Telephone mute input
63 P24/ANI4 PREMOTE I/O O CMOS External amp on
64 P23/ANI3 PPWR I/O O CMOS Power on
65 P22/ANI2 PRDS_DI I/O I - From tuner pack, RDS data input
66 P21/ANI1 PDIM_IN I/O I - Dimmer input
67 P20/ANI0 PEEPROM_CE I/O O CMOS EEPROM Chip select
68 P130 PPLL_CE O O CMOS PLL chip select
69 P131/TI06/TO06 PSD_ST I/O I - SD level input from Tuner pack
70 P04/SCK10'/SCL1 PART_EN I/O O - ART Enable input
71 P03/SI10/RxD1/SDA1 PART_RX I/O I - Data input for ART
72 P02/SO10/TXD1 PART_TX I/O I CMOS Data output for ART
73 P01/TO00 PFRT_DETECT I/O I - Front detaching/attaching detect
74 P00/TI00 PFRT_OPEN I/O I - Front open/close detect
75 P145/TI07/TO07 PFRT_RST I/O O CMOS Front micom(LCD drv) reset
76 P144/SO20/TxD2 PCDP_DO I/O O CMOS Data output for CDP
77 P143/SI20/RxD2/SDA2 PCDP_DI I/O I - Data input for CDP
78 P142/SCK20'/SCL2 PCDP_CLK I/O O CMOS CLK output for CDP
79 P141/PCLBUZ1/INTP7 PFRT_CE I/O I - Data enable output to front micom(LCD drv)
80 P140/PCLBUZ0/INTP6 PBEEP I/O O CMOS Buzzer output
81 P120/INTP0/EXLVI PEXLVI I/O I - Low voltage detector(Connect to Vdd)
82 P47/INTP2 PFLMD0_ CTR I/O O CMOS
Disc download FLMD0 control(Connect to
FLMD0(Pin93))
83 P46/INTP1/TI05/TO05 PRDS_CLK I/O I - From tuner pack, RDS data input
84 P45/SO01 PFRT_DO I/O O CMOS Data output to front micom(LCD drv)
85 P44/SI01 PFRT_DI I/O I - Data input from front micom(LCD drv)
86 P43/SCK01' PFRT_CLK I/O O CMOS CLK output to front micom(LCD drv)
87 P42/TI04/TO04 PANT I/O O CMOS Antena control output
88 P41/TOOL1 Download_CLK I/O - - CLK for onboard debugger
89 P40/TOOL0 Download_IO I/O - -
Data I/O for flash memory programmer
(Pull-up register(10K))
90 RESET' - - - - System reset input
91 P124/XT2 - I I - Sub clock 32.768 KHz
92 P123/XT1 - I I - Sub clock 32.768 KHz
93 FLMD0 - Flash memory programming mode setting
94 P122/X2/EXCLK - I I - X-tal 19.2 MHz
95 P121/X1 - I I - X-tal 19.2 MHz
96 REGC - - Connect to VSS via a capacitor (0.47 to 1µF)
97 VSS - Ground
98 EVSS0 - Ground Potential for Ports
99 VDD - Positive power supply (+5V)
100 EVDD0 - Positive power supply (+5V) For Ports
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