LG L601i, Руководство по обслуживанию

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3.4 LO Phase-locked Loop
Most LO functions are fully integrated on-chip, do not require user adjustment, and need not be
considered by handset designers. QUALCOMM has established and implemented frequency plans
and LO generation schemes that support the radioOne 6250-IIseries chipset while requiring minimal
off-chip design effort. Only one area requires handset designer attention: the loop filters of each
phase-locked loop (PLL).
3.4.1 UMTS Receiver LO generation
All the active circuits necessary for generating the UMTS LO are integrated within the RFR6250 IC;
only the passive loop filter is off-chip. The UMTS PLL and VCO are automatically disabled when the
handset is not processing UMTS signals.
All the UMTS PLL circuits are contained within the RFR6250 IC: reference divider, phase detector,
charge pump, feedback divider, and digital logic that generate lock status.
The VC-TCXO signal provides the synthesizer input (TCXO), the frequency reference to which the PLL
is phase and frequency locked. The reference is divided by the R-counter to create a fixed frequency
input to the phase detector, FR. The other phase detector input (FV) varies as the loop acquires lock,
and is generated by dividing the VCO frequency using the feedback path’s N-counter.
The closed loop will force FV to equal FR when locked. If the loop is not locked the error between FV
and FR will create an error signal at the output of the charge pump. This error signal is filtered by the
external loop filter and applied to the UMTS VCO (at UMTS_TUNE on the RFR6250 IC), tuning the
output frequency such that the error is decreased. Ultimately, the loop forces the error to approach
zero and the PLL is phase and frequency locked.
3. TECHNICAL BRIEF
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Figure 3.4.1-1 UMTS Rx PLL functional block diagram
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