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3. TECHNICAL BRIEF
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ͽͶ͑ͺΟΥΖΣΟΒΝ͑ΆΤΖ͑ΟΝΪ
3.6 MEMORY(K5N3217ATA-AT80, U102 )
The K5N3217ATA is a MultiChip Package Memory which combines 32Mbit MuxNOR Flash Memory and 16M bit
MuxUtRAM2. The 32Mb NOR Flash featuring single 1.8V power supply is 32Mbit Synchronous Burst Multi Bank
Flash Memory organized as 2Mx16. The memory architecture of the device is designed to divide its memory
arrays into 71 blocks with independent hardware protection. This block architecture provides highly flexible
erase and program capability. The 32Mb NOR Flash consists of sixteen banks. This device is capable of reading
data from one bank while programming or erasing in the other bank. Regarding read access time, the device
provides an 14.5ns burst access time and an 70ns initial access time at 54MHz. At 66MHz, the device provides
an 11ns burst access time and 70ns initial access time. At 83MHz, the device provides an 9ns burst access time
and 70ns initial access time.
Figure. 3.6.1 MEMORY BLOCK DIAGRAM
3. TECHNICAL BRIEF