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Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
4. RF Circuit Technical Brief
GM310f service manual
4.3 WCDMA Part
The single-chip transceiver is designed to fulfill the W-CDMA UTRA FDD system requirements for
bands I, II, III, IV, V, VI and IX. It contains all active circuits required to simultaneously modulate an
analog W-CDMA I/Q signal to the TX RF frequency and demodulate a RX RF W-CDMA signal to an
I/Q baseband signal.
4.3.1 WCDMA Receiver
The direct conversion receiver for each band consists of:
•fully differential signal path
•RF low noise amplifier (LNA)
•I/Q demodulator including LO buffer and I/Q divider
•LO including on-chip VCO and synthesizer
•DC offset compensation without external components
•analog channel filter including auto calibration circuit (w/o external components)
•programmable gain control (PGC) controlled by 3-wire bus programming and gain setting unit on-chip
•allpass filter (auto calibrated)
•configurable output drivers (programmable DC voltages and driver currents for different load
impedances)
RX Front-End
An external low noise amplifier as well as duplex and inter-stage filters are needed to form a complete
receive chain for each band.
Baseband Processing (analog)
The amplified RF signal is converted by a quadrature demodulator to I and Q signals at baseband
frequency. The resulting inphase and quadrature signals are fed into the analog baseband low pass
filter (Chebyshev type). An optional, additional filter stage can be activated in order to provide the
required selectivity for narrowband blockers. The filter corner frequency is controlled by an on-chip
filter alignment circuit. This filter also provides the overall baseband PGC functionality. The differential
offset voltage after the demodulator is reduced by an on-chip DC compensation loop. The subsequent
last PGC amplifier stage provides 1 dB gain steps. All gains are selected by 3-wire bus program-ming.
Содержание GM310
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