43
URDY
111
O
PU/TS
System Controller-RAM Transfer Ready:
This signal is asserted low to
extend a system controller-RAM access until the RAM data is ready to be
read or written. If direct-RAM access is used (UCS1# asserted), a system
controller with a wait-state insertion input must be used. For RAMRD/
RAMWR (01Eh) accesses (UCS0# asserted), URDY can also be used to
extend accesses of the RAMRD and RAMWR registers if bit URDY0E
(0D5h.4) = 1. Bit URDYZb (0C8h.5) controls whether URDY is Hi-Z when
UCS1# and UCS0# are de-asserted. URDY is default Hi-Z when neither
chip select is asserted, therefore a pull-up resistor must be used with URDY.
Bit URDYMOD (0C8h.4) controls whether URDY is high or low when the
data strobes are inactive.
UCS0#
107
I
S
System Controller Chip Select 0:
When UCS0# is asserted, the system
controller can address the internal registers.
UCS1#
110
I
S
System Controller Chip Select 1:
When UCS1# is asserted, the system
controller can address the RAM directly.
SDINT#
114
O
PU
CD-DSP / CD-Servo Interrupt Request
CLKOUT /
ARST#
65
O
OD
ATAPI Reset Interrupt Request or Output:
OTI-9797 asserts ARST# when
the host has written the ATAPI Soft Reset Command (08h). ARST#
(enabled
when bit ARSTEN (02Fh.3) = 1) can be used as an interrupt
request output (if ARSTS (02Fh.2) = 1) or a reset output pulse. ARST# is
cleared for interrupt operation by writing to register ARSTACK (030h).
UINT0#
112
O
PU
CD-Decoder/Encoder Interrupt Request 0
UINT1#
113
O
PU
CD-Decoder/Encoder Interrupt Request 1
UALE
115
I
S
Address Latch Enable:
In multiplexed mode, UALE indicates that UAD7 0
contains a valid address. UALE must be grounded to enable non-
multiplexed mode.
PRST#
96
I
S
Power-on Reset:
Forcing this input low resets the device.
RD13 /
CPUTYPE
19
I/O
PU
CPU Type Select:
When HRST# or PRST# is asserted, this signal selects
whether the System Controller Interface is configured for Motorola (if
CPUTYPE is low) or x86 Mode (if CPUTYPE is high). After reset this
signal is used as RD13 for the buffer interface.
Pin Name
Pin #
Typ e
Description