LG G1610, Руководство по обслуживанию

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3. TECHNICAL BRIEF
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3.8 Memory (U300)
The memory is consists of 128Mbit Nor Flash Memory and 32Mbit Pseudo SRAM. It has 16 bit
parallel data bus and 22 bit address.
Software, RF calibration data, audio parameters and battery calibration data are stored in the
Flash memory.
Figure 3-13 Block Diagram of Memory
Figure 3-8 Pin Description of U300
128 Mbits
FLASH Memory
32 Mbits
PSEUDO SRAM
A-1 A0~A21
Vccf Vss
Vss Vccps
DQ0~DQ15
(DQ~DQ7)
DQ0~DQ15
DQ0~DQ15
A0~A20
A-1, A0~A21
WP/ACC
RESET
CEf1
CEf2
RY/BYf
BYTE
WE
OE
CE1ps
CE2ps
UB
LB
A-1, A0 to A21
Address inputs
Data inputs / outputs
Chip enable inputs for Pseudo SRAM
Chip enable inputs for Nor Flash Memory
Output enable input
Write enable input
Data byte control inputs for Pseudo SRAM
Write protect /program acceleration input Nor Flash Memory
Hardware reset input for Nor Flash Memory
Word/Byte select input for Nor Flash Memory
Ready/Busy output for Nor Flash Memory
Power supply for Pseudo SRAM
Power supply for Nor Flash MemoryPseudo SRAM
Ground
Donʼt use
Not connected
DQ0 to DQ15
CE1ps , CE2ps
CEf1 , CEf2
OE
WE
LB , UB
WP/ACC
RESET
BYTE
RY/BY f
Vccps
Vccf
Vss
DU
NC