SR[23]
SR[20]
SR[27]
AUX2[3]
UDAC/YUV0
COMP/YUV3
IDAC/YUV1
YDAC/YUV5
VD33DAC
FDAC/YUV7
VD33
AUX3[0]/CAMIN0
AUX3[2]/CAMIN2
VDD
AUX3[5]/CAMIN5
AUX3[7]/CAMIN7
AUX15/656CLK
VS33
AUX10/TSD[3]
CDAC/YUV2
VS33DAC
VDAC/YUV6
RSET/YUV4
VS33
AUX3[1]/CAMIN1
AUX3[3]/CAMIN3
AUX3[4]/CAMIN4
AUX3[6]/CAMIN6
AUX2[3]
AUX12/RBCK/TDMCL
AUX11/RSD/TDMDR
AUX8/VSYNC/RXD2
VREF
SR[21]
SR[26]
SR[22]
CLK/TDMCLK/RBCK
RESET#
MCLK
AUX9/HSYNC/TXD2
VD33
SPI_CLK
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
ES8391
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
205
206
207
208
209
210
211
212
213
214
215
216
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
10
9
11
0
53
54
55
56
57
58
59
60
61
62
63
64
65
66
F
DRFP
SLV
MIN
H
G
DRFN
VGA
DMO
FOO
DRAS2#
SR[16]
SR[15]
SLO
SR[17]
VD33
DMA2
TRO
AUX2[6]
VS33
DMA1
CDPD
SR[13]
DMA4
DMA6
DMA0
VPA
REFD
SR[14]
DMA5
DMA7
DMA10
A
D
E
DRAS1#
VB
O
SP
N
N
/M
N
T
R
N
S
P
N
P
/M
N
T
R
P
/I
M
S
R
AG
C
1
DV
DLD
CDLD
S
R
[37]
S
R
[36]
S
R
[35]
VI
D
_
X
I
IN
V
_
O
U
T
RE
X
AG
C
2
DV
DP
D
PI
V
165O
O
PEN
O
PEN
SW
AU
X2
[4
]
S
R
[30]
S
R
[31]
S
R
[34]
TE
FE
MB
DB
MP
VG
B
VP
B
S
R
[32]
VI
D
_
X
O
VD
D
T
B
CK
/P
W
M
_01
R/DA
C_O
1
R
T
S
D
3
/P
W
M
_O
3R/DAC_O
3R
T
S
D2/
P
W
M
_O
3L/
D
A
C
_
O
3
L
US
B
_
P
0
AV
D
3
3
US
B
_
N0
AD
C
_
BI
AS
S
R
[33]
DB
1
DB
2
SR
[0
3
]
DB
0
SR
[0
4
]
SR
[0
0
]
SR
[0
1
]
AU
X4
VD
3
3
DB
13
DB
12
DB
1
1
DB
14
SR
[0
2
]
VD
3
3
DB
5
DQ
M
DCA
S
#
/S
E
L_P
LL3
VD
3
3
DO
E
#
/S
E
L_P
LL0
D
W
E
#
/S
E
L_P
LL1
DS
CK
DB
6
VS
3
3
DB
7
DB
9
DB
10
VD
D
VS
3
3
DB
8
AU
X7
AU
X6
AU
X5
SR
[0
5
]
SR
[0
6
]
VS
3
3
VD
D
AU
X3
AU
X2
AU
X1
SPI
_CS3
VD
3
3
SPI
_CS2
AU
X0
AU
X2
[1
]
SR
[0
7
]
VS33
DC
S
1
#
DCS
0
#
DR
A
S
0
#
/S
E
L_P
LL2
DB
4
DB
3
DB
15
AU
X2
[0
]
CLO
S
E
C
L
O
SESW
AM
PS
T
B
Y
LDCO
VD
3
3
VS
3
3
VS
3
3
VD
3
3
T
S
D
1
/P
W
M
_O
2R/DAC_O
2R
T
S
D0/
P
W
M
_O
2L/
D
A
C
_
O
2
L
T
W
S/
PWM_O
1
L
/D
A
C
_
O
1
L
A
VS3
3
MI
C
_
R
MI
C
_
L
VS33PLL
VD33PLL
SR[24]
SR[25]
VS33
VD33
AUX14/TBCK/TXD1
AUX13/RWS/TDMFS
SPDIF_OUT
SPI_DO
SPI_DI
B
C
AVD33
AVS33
DVCC
VD33
VS33
VDD
SIN
SOUT
AUX2[5]
SR[10]
SR[11]
SR[12]
DMA3
DMA11
DMA9
DMA8
SPDIF_IN
3-55
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
• ES8391
1) PIN CONFIGURATION