THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
15-06-13
MAIN4_EXT_IN/OUTPUT
06
K2L
TXDBP6_L
COMP1_PbP
TXDBN2_L
EO_A
TXDAP5_L
BIT5
TXDAN1_L
R613
100
DATA_FORMAT_0
C630
0.047uF
TXDAP2_L
SC_CVBS_IN
COMP1_PrP
DTV/MNT_V_OUT
TXDBN7_L
COMP1_PrP
TXDBP2_L
GCLK_A
TXDAN6_L
GCLK_A
BIT6
TXDAP1_L
/USB_OCD3_0
DATA_FORMAT_1
AMP_RESET_N
EO_A
COMP1_Y/CVBS
TXDAN3_L
COMP1_YPbPrN
TXDBN4_L
COMP1_Y/CVBSP
TXDBP7_L
C635
0.047uF
TXDBN3_L
I2C_SCL6
TXDAP6_L
R615
100
BIT7
USB_CTL3_0
L600
PZ1608U121-2R0TF
BIT9
C629
0.047uF
TXDAP3_L
C605
5pF
50V
TXDBP4_L
C604
5pF
50V
TXDBN0_L
C606
5pF
50V
TXDBP3_L
MCLK_A
I2C_SDA6
TXDAN7_L
R610
100
BIT8
L601
PZ1608U121-2R0TF
VID_CPU
COMP1_Pb
C633
0.047uF
COMP1/AV1/DVI_R_IN
COMP1_YPbPrN
TXDBN5_L
COMP1_YPbPrN
TXDBP0_L
TXDAN4_L
GST_A
BIT0
TXDAP7_L
R611
100
L/D_CLK
DTV/MNT_V_OUT
VID_CORE
C631
0.047uF
TU_CVBS
COMP1/AV1/DVI_L_IN
C603
5pF
50V
TXDBP5_L
TXDBN1_L
GST_A
TXDAP4_L
LOCKAn
TXDAN0_L
R614
100
L/D_DO
C656
1uF
C657
0.1uF
16V
COMP1_Pr
COMP1_YPbPrN
HP_LOUT
COMP1_PbP
TXDBN6_L
COMP1_Y/CVBSP
TXDBP1_L
MCLK_A
TXDAN5_L
HTPDAn
TXDAP0_L
R612
100
L/D_VSYNC
TXDAN2_L
C634
0.047uF
C632
0.047uF
HP_ROUT
C654
2.2uF
C655
2.2uF
IC100
LGE6551_AA1
LVDS_AAN
J1
LVDS_AAP
J2
LVDS_ABN
K1
LVDS_ABP
K2
LVDS_ACN
L1
LVDS_ACP
L2
LVDS_ADN
M1
LVDS_ADP
M2
LVDS_AEN
N1
LVDS_AEP
N2
LVDS_AFN
P1
LVDS_AFP
P2
LVDS_BAN
AK38
LVDS_BAP
AK37
LVDS_BBN
AK36
LVDS_BBP
AL37
LVDS_BCN
AL36
LVDS_BCP
AM37
LVDS_BDN
AM38
LVDS_BDP
AM36
LVDS_BEN
G1
LVDS_BEP
G2
LVDS_BFN
H1
LVDS_BFP
H2
LVDS_CAN
E1
LVDS_CAP
E2
LVDS_CBN
F1
LVDS_CBP
F2
LVDS_CCN
AG38
LVDS_CCP
AG37
LVDS_CDN
AG36
LVDS_CDP
AH37
LVDS_CEN
AH36
LVDS_CEP
AJ37
LVDS_CFN
AJ38
LVDS_CFP
AJ36
LVDS_DAN
B4
LVDS_DAP
A4
LVDS_DBN
B3
LVDS_DBP
A3
LVDS_DCN
A1
LVDS_DCP
A2
LVDS_DDN
B1
LVDS_DDP
B2
LVDS_DEN
C1
LVDS_DEP
C2
LVDS_DFN
D1
LVDS_DFP
D2
IC100
LGE6551_AA1
VINRP
AE2
VINRN
AE3
VINGP
AD2
VINGN
AD1
VINBP
AD3
VINBN
AC1
VSYNC
AB2
HSYNC
AC3
VIN3P
AF1
VIN4P
AF3
VIN5P
AG3
VINY0N
AF2
VIN10P
AG1
VIN13P
AG2
VINA0N
AH3
AI1L
AK3
AI1R
AK1
AI2L
AK2
AI2R
AL3
AI3L
AL2
AI3R
AM3
AI4L
AM2
AI4R
AM1
AIO2L
AN3
AIO2R
AN1
HPOL
AN2
HPOR
AP3
VDACOUT
AJ3
VDBSOUT
AJ2
FSW0
AH2
SPDIF_OUT
AG4
MICBAIS
AF4
ADCG
AG5
BBG
AR3
VCMBB
AP2
R616
100
R617
100
R618
100
Level Shifter
Internal Analog Demod Test Point
EPI Share Lane
For 51p location
GND pattern should be
connected with 75ohm reg
of Component Jack
EPI Share Lane
For 41p location
GND pattern should be
connected with 75ohm reg
of SCART Jack
port changed
(SPDIF noise issue)
Close to Main chip
Level Shifter
Copyright © 2016 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Содержание EA71G
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