ADCVDD
VBDPLL
PLLVSS
LPIO
LPIN
LPFO
LPFN
IREF
PDO
PLLVDD
UP3_5/UT1
UP3_4/UT0
DGND
UP3_2/UINT0
UP3_1/UTXD
UP3_0/URXD
DVDD
IO5
IO6
IO7
IO8
LED
EJECT_
PLAY_
UP1_0/UA16
UP2_7/UA15
UP3_6/UWR_
UP2_6/UA14
UP2_5/UA13
UP2_4/UA12
UP2_3/UA11
UP2_1/UA9
UPSEN_/O9
UP2_0/UA8
UP0_7/UAD7
UP0_6/UAD6
UP0_5/UAD5
UP0_4/UAD4
UP0_3/UAD3
UP0_2/UAD2
UP0_1/UAD1
DGND
UP2_2/UA10
UALE/IO10
IO4/CS_
UP0_0/UAD0
UA0/O1
1
UA1/O12
UA2/O13
UA3/O14
UA4/O15
UA5/O16
UA6/O17
UA7/O18
XTLI
XTLO
DVDD
DGND
RD15
RD0
RD14
RD1
RD13
RD2
DVDD3
RD12
RD3
RD1
1
RD4
RD10
RD5
RD9
RD6
RD8
RD7
CASL_
CASH_
R
WE_
RAS_
DVDD
RA8
RA7
RA0
RA6
RA1
RA5
RA2
RA4
RA3
SCO
RFDTSL
V
ADCVSS
RFI
RFIS
RFBIAS
HRFZC
RFRPSL
V
RFRO
FEI
TEI
TEZI
TEZILP
SBAD
PDMVDD
FOO
TRO
PDMVSS
PWM2VREF
PWMVREF
RFGC
TEBC
DMO
ENDM
FMO2
FMO
LDC
FG
POR
IO1
IO0
DGND
DVDD3
LIMIT_
TRCLOSE
TROPEN
TRA
YOUT_
TRA
YIN_
DGND
IPLL
VSS
IPLL
VDD
HRST_
DD7
DDS
DD6
DVDD
DD9
DD5
DD10
DD4
DD11
DD3
DD12
DGND
DD2
DD13
DD1
DD14
DD0
DD15
DMARQ_
DIOW_
DIOR_
IORDY
DMACK_
INTRQ
IOCS16_
DVDD
DA1
PDIAG_
DA0
DA2
DGND
CSIFX_
CS3FX_
DASP_
DEVSEL
VPVSS
VCOCIN
VPVDD
DACVDD
LO
DACVREF
RO
DACVSS
ADGO/VIO0
DGND
Data Slicer
and Data PLL
RFRP
Circuit
Servo
ADC
Servo
DSP
PDM &
PWM
DAC
Reset
Circuitry
Host
Data FIFO
RSPC
Decoding
Logic
DSP Data
FIFO/
Parallelizer
Descrambler
Audio
Processing
Unit
Audio
Playback
Logic
CIRC Error
Correction
EFM & Q-code
Demodulation
Mega
Interface
and
GPIO
Control
Sync
Protection
CLV & Zone-
CLV & True-
CAV Control
Subcode
FIFO/
Parallelizer
8032
Micro processor
GPIO
Control
X’tal Clock
Generator
Buffer Memory Controller
ATAPI
Packet
FIFO
Digital Emphasis
Varipitch
Clock
Generator
DAC &
LPF
Over-sampling
Digital Filter
RSPC
Sync
Detector
Host
Interface
Logic
Mega interface
and GPIO Control
1PLL
Decoder & UP
Clock Generator
16
• IC501 (MT1198CE) : DSP+ATAPI µ-COM
Block Diagram