17
120
CS3FX_
TTL Input, SMT
50K pull_up
Device Chip Select 1. This is the chip select signal from the host to
select the Control Block Registers.
121
CS1FX_
TTL Input, SMT
50K pull_up
Device Chip Select 0. This is the chip select signal from the host to
select the Command Block Registers.
122
DGND
Ground
Ground pin for internal digital circuitry.
123,127,124
DA[2:0]
TTL Input, SMT
50K pull_up
Device Address. This is the 3-bit binary coded address provided by
the host to access an ATA register or data.
125
DVDD3
Power(3.3V)
3.3V power pin for digital circuitry.
126
PDIAG_
TTL Input,
50K pull_up
Passed Diagnostics. This signal is asserted by Device 1 to indicate
to Device 0 that it has completed diagnostics.
128
DVDD
Power(5V)
Power pin for internal digital circuitry.
129
IOCS16_
TTL Output
Open drain
Device 16-BIT I/O. In PIO transfer modes 0, 1, and 2, IOCS16_
indicates to the host system that the 16-bit data port has been
addressed and that the device is prepared to send or receive a 16-
bit data word. The MT1199 will always assert IOCS16_ when the
host reads the ATAPI Data Register.
130
INTRQ
TTL I/O
Slew rate
Device Interrupt. This signal is used to interrupt the host system.
INTRQ is driven only when the MT1199 is addressed, i.e.,
DRV101h.RW7=DRV16h.RW4. When not driven, INTRQ is in a
high impedance state.
131
DMACK_
TTL Input, SMT
50K pull_up
DMA Acknowledge. This signal shall be used by the host in
response to DMARQ to acknowledge that it is ready for DMA
transfers.
132
IORDY
TTL Outout
Slew rate
I/O Channel Ready. This signal is negated (pulled low) during PIO
to extend the host transfer cycle of any host register access (Read
or Write) when the MT1199 is not ready to respond to a data
transfer request. When IORDY is not negated, it is in a high
impedance state. In Ultra DMA transfers, the signal becomes either
DDMARDY_ (Device Ultra DMA Ready) that is asserted by the
MT1199 to indicate to the host that it is ready to receive data, or
DSTROBE (Device Ultra DMA Data Strobe) whose rising edge and
falling edge latch the data from DD0–DD15 into the host.
133
DIOR_
TTL Input, SMT
50K pull_up
Device I/O Read. This is the ATA read strobe signal. In PIO or
multiword-DMA the falling edge of DIOR_ enables data from the
MT1199 onto the host data bus, DD0–DD7 or DD0–DD15. The
rising edge of DIOR_ then latches the data at the host. During Ultra
DMA transfers the signal becomes either HDMARDY_ (Host Ultra
DMA Ready), which is asserted by the host to indicate to the
MT1199 that the host is ready to receive data, or HSTROBE (Host
Ultra DMA Data Strobe), whose rising edge and falling edge latch
the data from DD0–DD15 into the MT1199.
134
DIOW_
TTL Input, SMT
50K pull_up
Device I/O Write. This is the ATA write strobe signal. In PIO or
multiword-DMA the rising edge of DIOW_ latches data from the
host data bus, DD0–DD7 or DD0–DD15, into the ATA registers or
the ATAPI Packet FIFO of the MT1199. In Ultra DMA transfers the
signal becomes STOP (Stop Ultra DMA Data Transfer), which is
negated by the host before data can be transferred by an Ultra
DMA burst, and asserted by the host when it want to terminate an
Ultra DMA burst.
135
DMARQ
TTL Output
DMA Request. This signal, used for DMA data transfer, is asserted
by the MT1199 when it is ready to transfer data to or from the host.
