THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
M1_DDR_A5
M0_DDR_CASN
M1_DDR_WEN
C535
0.1uF
M1_DDR_DQ30
M0_DDR_VREFDQ
M1_DDR_DQS_N1
M1_DDR_DQS0
M1_DDR_A13
M1_DDR_DQ28
M1_DDR_DQ29
M1_DDR_DQ4
M0_DDR_DQ11
C561
0.1uF
M1_DDR_CKE
M1_DDR_A6
M0_DDR_A4
+1.5V_DDR
M0_DDR_DQ10
M0_DDR_A3
M1_DDR_RASN
R544
240
1%
M0_DDR_DQ26
M0_DDR_DQ25
R513
1K
1%
M1_DDR_DQ3
M0_DDR_A6
M0_DDR_DM2
M1_DDR_DQ14
M1_DDR_DQS_N0
M0_DDR_A6
M0_DDR_DQ27
M0_DDR_A11
M1_DDR_A14
M0_DDR_A2
M1_DDR_DQ12
M0_U_CLKN
M0_DDR_VREFCA
M1_DDR_DQ15
M0_DDR_DQ23
M1_DDR_DQ13
+1.5V_DDR
M1_DDR_DM3
M1_1_DDR_VREFCA
M1_DDR_A11
M1_D_CLKN
M0_DDR_A7
M0_DDR_A12
M0_1_DDR_VREFDQ
M0_DDR_DQS1
R516
1K
1%
M0_DDR_A11
+1.5V_DDR
R
5
1
8
1
0
0
R514
1K
1%
M1_DDR_DQS1
M1_DDR_DQS3
M1_DDR_CKE
M0_DDR_CASN
M1_DDR_A7
M0_DDR_BA0
M0_DDR_DQS_N0
M0_DDR_A1
M1_DDR_A1
M1_DDR_BA2
M0_DDR_DQS_N2
M0_DDR_DM1
M1_DDR_A11
M0_D_CLKN
M1_DDR_A0
M1_1_DDR_VREFDQ
R538
1K
1%
M0_DDR_DQ18
M0_DDR_DQ0
M1_DDR_A8
M0_DDR_BA2
+1.5V_DDR
M0_DDR_DQ24
R532
1K
1%
M1_DDR_BA0
M0_DDR_A8
M1_DDR_A2
M1_DDR_A6
M0_U_CLK
R533
1K
1%
M0_DDR_VREFDQ
M1_DDR_VREFDQ
+1.5V_DDR
M1_DDR_A9
M1_DDR_DQ16
M0_DDR_DQ29
M1_DDR_A12
M1_DDR_A5
+1.5V_DDR
M1_U_CLKN
M0_DDR_DM0
C566
0.1uF
M0_DDR_A2
M1_DDR_A3
M1_DDR_DQ8
M0_DDR_DQ9
R501
240
1%
M1_D_CLK
M0_DDR_BA0
M1_DDR_DM2
M0_DDR_DQ30
M1_DDR_VREFCA
M0_D_CLK
C530
0.1uF
M0_DDR_A2
M1_DDR_A13
M0_DDR_BA0
M1_DDR_CASN
M0_1_DDR_VREFCA
R545
240
M0_DDR_DQ17
M0_DDR_DQ15
M1_DDR_A1
M0_DDR_ODT
M1_DDR_BA1
M1_DDR_DQ25
M0_DDR_WEN
M1_DDR_VREFDQ
M0_DDR_DQ2
M1_DDR_A7
M1_DDR_DQ21
M0_1_DDR_VREFCA
M0_DDR_A4
M1_DDR_A11
C529
0.1uF
C567
0.1uF
M0_DDR_DQ14
M1_DDR_DM0
M1_DDR_A0
M0_DDR_A0
M0_DDR_DQS_N1
M1_DDR_DQ10
M1_DDR_A5
M1_U_CLK
M1_DDR_DQ18
M0_DDR_VREFCA
R
5
3
5
1
0
0
M0_DDR_DQ6
M1_DDR_A7
M1_D_CLKN
M0_DDR_DQ21
+1.5V_DDR
M0_DDR_A10
M1_DDR_DQ7
M1_U_CLK
M1_DDR_DQ2
M1_DDR_A10
M0_DDR_A8
M0_DDR_DQ1
M0_DDR_DQS2
M0_DDR_A13
M1_DDR_DQ17
R537
1K
1%
M1_DDR_A10
M1_DDR_A8
M1_DDR_BA1
M1_DDR_DQS_N2
M1_U_CLKN
M0_DDR_A5
M0_DDR_DM3
M0_DDR_DQ19
+1.5V_DDR
R512
1K
1%
M0_U_CLKN
M0_DDR_DQ22
M1_DDR_A13
M1_DDR_BA2
M0_DDR_BA1
M0_DDR_A9
M0_DDR_A4
M1_DDR_A4
M1_DDR_DQ5
M1_DDR_A9
M0_DDR_CKE
M0_DDR_DQ16
M0_DDR_A9
M1_DDR_DM1
M0_DDR_DQ5
M1_DDR_A1
R539
1K
1%
M0_U_CLKN
+1.5V_DDR
M0_1_DDR_VREFDQ
M0_DDR_DQ8
M1_1_DDR_VREFCA
M0_D_CLK
M0_DDR_DQ7
M1_DDR_A3
M0_DDR_RASN
M1_DDR_A14
R511
1K
1%
M0_DDR_WEN
M1_DDR_A2
M0_DDR_A14
M1_DDR_A8
M0_DDR_DQ28
M0_DDR_DQS_N3
R536
1K
1%
M1_DDR_DQ11
M1_DDR_DQ6
M0_DDR_A6
M1_DDR_VREFCA
M0_DDR_DQ3
M0_DDR_A5
M0_DDR_DQ4
M1_DDR_BA0
M0_DDR_A14
R510
1K
1%
M1_DDR_DQ26
M1_DDR_A0
M0_D_CLKN
M1_DDR_A4
M0_DDR_A1
+1.5V_DDR
M0_DDR_A0
M1_DDR_DQ22
M0_DDR_CKE
M1_DDR_A2
M1_DDR_A3
M1_D_CLK
M0_DDR_A12
M0_U_CLK
M1_D_CLK
M0_DDR_A10
R515
1K
1%
M0_DDR_DQ31
M0_DDR_ODT
M0_DDR_RESET_N
M0_DDR_A0
M1_DDR_RESET_N
M1_DDR_ODT
M1_DDR_DQ19
R517
1K
1%
M1_DDR_CASN
M0_DDR_A13
M0_D_CLK
M0_DDR_DQS3
R531
1K
1%
M1_DDR_DQ1
M1_DDR_A12
M0_DDR_DQ13
M1_DDR_A9
M0_DDR_A13
M0_DDR_BA2
M1_DDR_BA1
M1_DDR_DQ9
M0_DDR_A5
C562
0.1uF
M0_DDR_A9
M1_D_CLKN
M0_DDR_DQS0
M1_DDR_DQ0
M1_DDR_BA2
R
5
1
9
1
0
0
M1_DDR_DQ23
M1_DDR_ODT
M1_DDR_DQ27
M0_U_CLK
M0_DDR_A1
M0_DDR_BA1
M1_DDR_A10
M1_DDR_DQ24
M0_DDR_A10
R
5
3
0
1
0
0
M0_DDR_DQ20
M1_DDR_A14
+1.5V_DDR
M0_DDR_A3
M1_DDR_BA0
M1_DDR_DQS_N3
M1_DDR_A6
M1_DDR_RESET_N
M0_DDR_RASN
M0_DDR_A7
M0_DDR_RESET_N
R500
240
1%
M0_DDR_BA1
M1_DDR_DQ20
M1_U_CLK
M1_1_DDR_VREFDQ
M1_DDR_DQ31
M1_DDR_A12
R543
240
M0_DDR_A8
M0_DDR_A7
M0_DDR_DQ12
+1.5V_DDR
M1_U_CLKN
M1_DDR_DQS2
M1_DDR_WEN
M0_DDR_A12
M0_DDR_A14
M1_DDR_RASN
R534
1K
1%
M0_D_CLKN
M1_DDR_A4
R542
240
1%
M0_DDR_BA2
M0_DDR_A11
M0_DDR_A3
C534
0.1uF
M0_CS0_N
M0_CS0_N
M1_CS0_N
M1_CS0_N
M1_DDR_DQ18
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ16
M1_DDR_DQ0
M1_DDR_DQ14
M1_DDR_DQ26
M1_DDR_DQ8
M1_DDR_DQ15
M1_DDR_DQ29
M1_DDR_DQ31
M1_DDR_DQ3
M1_DDR_DQ28
M1_DDR_DQ24
M1_DDR_DQ13
M1_DDR_DQ23
M1_DDR_DQ11
M1_DDR_DQ21
M1_DDR_DQ7
M1_DDR_DQ17
M1_DDR_DQ20
M1_DDR_DQ22
M1_DDR_DQ9
M1_DDR_DQ30
M1_DDR_DQ6
M1_DDR_DQ12
M1_DDR_DQ25
M1_DDR_DQ1
M1_DDR_DQ10
M1_DDR_DQ27
M1_DDR_DQ19
M1_DDR_DQ2
M1_DDR_DM0
M1_DDR_DM1
M1_DDR_DM2
M1_DDR_DM3
M1_DDR_DQS_N2
M1_DDR_DQS3
M1_DDR_DQS_N0
M1_DDR_DQS0
M1_DDR_DQS2
M1_DDR_DQS_N3
M1_DDR_DQS1
M1_DDR_DQS_N1
M1_DDR_RASN
M1_DDR_ODT
M1_DDR_WEN
M1_DDR_CASN
M1_CS0_N
M0_DDR_DQ28
M0_DDR_DQ10
M0_DDR_DQ20
M0_DDR_DQ3
M0_DDR_DQ2
M0_DDR_DQ9
M0_DDR_DQ17
M0_DDR_DQ27
M0_DDR_DQ30
M0_DDR_DQ1
M0_DDR_DQ0
M0_DDR_DQ13
M0_DDR_DQ23
M0_DDR_DQ22
M0_DDR_DQ12
M0_DDR_DQ11
M0_DDR_DQ14
M0_DDR_DQ5
M0_DDR_DQ8
M0_DDR_DQ15
M0_DDR_DQ18
M0_DDR_DQ19
M0_DDR_DQ4
M0_DDR_DQ6
M0_DDR_DQ26
M0_DDR_DQ29
M0_DDR_DQ24
M0_DDR_DQ25
M0_DDR_DQ31
M0_DDR_DQ7
M0_DDR_DQ16
M0_DDR_DQ21
M0_DDR_DM1
M0_DDR_DM3
M0_DDR_DM0
M0_DDR_DM2
M0_DDR_DQS2
M0_DDR_DQS1
M0_DDR_DQS3
M0_DDR_DQS_N1
M0_DDR_DQS0
M0_DDR_DQS_N0
M0_DDR_DQS_N2
M0_DDR_DQS_N3
M0_CS0_N
M0_DDR_WEN
M0_DDR_ODT
M0_DDR_RASN
M0_DDR_CASN
M1_DDR_CKE
M0_DDR_CKE
DDR_RET
DDR_RET
R524
10K
Q500
MMBT3904(NXP)
E
B
C
INSTANT_BOOT
DDR_RET
+1.5V_DDR
R523
1K
C571
0.1uF
16V
C569
0.1uF
16V
+1.5V_DDR
C570
0.1uF
16V
+1.5V_DDR
C574
0.1uF
16V
C575
0.1uF
16V
C573
0.1uF
16V
IC100
LG1210D-B0(H15D-B0)
M0_DDR_A0
E29
M0_DDR_A1
E25
M0_DDR_A2
E31
M0_DDR_A3
E33
M0_DDR_A4
D23
M0_DDR_A5
D32
M0_DDR_A6
E23
M0_DDR_A7
E32
M0_DDR_A8
D24
M0_DDR_A9
E30
M0_DDR_A10
D22
M0_DDR_A11
D25
M0_DDR_A12
D26
M0_DDR_A13
D30
M0_DDR_A14
E24
M0_DDR_A15/M0_DDR_CS1
E34
M0_DDR_BA0
D33
M0_DDR_BA1
E22
M0_DDR_BA2
D29
M0_DDR_U_CLK
C26
M0_DDR_U_CLKN
B26
M0_DDR_D_CLK
C35
M0_DDR_D_CLKN
B35
M0_DDR_CKE
E26
M0_DDR_CS0
E27
M0_DDR_ODT
E35
M0_DDR_RASN
D35
M0_DDR_CASN
D34
M0_DDR_WEN
D27
M0_DDR_RESET_N
D31
M0_DDR_ZQCAL
C40
M0_DDR_DQS0
B36
M0_DDR_DQS_N0
C36
M0_DDR_DQS1
B34
M0_DDR_DQS_N1
A34
M0_DDR_DQS2
B27
M0_DDR_DQS_N2
C27
M0_DDR_DQS3
B25
M0_DDR_DQS_N3
A25
M0_DDR_DM0
A33
M0_DDR_DM1
A36
M0_DDR_DM2
A24
M0_DDR_DM3
A27
M0_DDR_DQ0
B38
M0_DDR_DQ1
B31
M0_DDR_DQ2
C39
M0_DDR_DQ3
C32
M0_DDR_DQ4
A39
M0_DDR_DQ5
A31
M0_DDR_DQ6
B39
M0_DDR_DQ7
C31
M0_DDR_DQ8
B32
M0_DDR_DQ9
B37
M0_DDR_DQ10
C33
M0_DDR_DQ11
C38
M0_DDR_DQ12
C34
M0_DDR_DQ13
A37
M0_DDR_DQ14
B33
M0_DDR_DQ15
C37
M0_DDR_DQ16
B29
M0_DDR_DQ17
C23
M0_DDR_DQ18
C30
M0_DDR_DQ19
B22
M0_DDR_DQ20
A30
M0_DDR_DQ21
A22
M0_DDR_DQ22
B30
M0_DDR_DQ23
C22
M0_DDR_DQ24
B23
M0_DDR_DQ25
B28
M0_DDR_DQ26
C24
M0_DDR_DQ27
C29
M0_DDR_DQ28
C25
M0_DDR_DQ29
A28
M0_DDR_DQ30
B24
M0_DDR_DQ31
C28
M0_RET
D21
IC100
LG1210D-B0(H15D-B0)
M1_DDR_A0
E13
M1_DDR_A1
E9
M1_DDR_A2
E15
M1_DDR_A3
E17
M1_DDR_A4
D7
M1_DDR_A5
D16
M1_DDR_A6
E7
M1_DDR_A7
E16
M1_DDR_A8
D8
M1_DDR_A9
E14
M1_DDR_A10
D6
M1_DDR_A11
D9
M1_DDR_A12
D10
M1_DDR_A13
D14
M1_DDR_A14
E8
M1_DDR_A15/M1_DDR_CS1
E18
M1_DDR_BA0
D17
M1_DDR_BA1
E6
M1_DDR_BA2
D13
M1_DDR_U_CLK
C6
M1_DDR_U_CLKN
B6
M1_DDR_D_CLK
C15
M1_DDR_D_CLKN
B15
M1_DDR_CKE
E10
M1_DDR_CS0
E11
M1_DDR_ODT
E19
M1_DDR_RASN
D19
M1_DDR_CASN
D18
M1_DDR_WEN
D11
M1_DDR_RESET_N
D15
M1_DDR_ZQCAL
B1
M1_DDR_DQS0
B16
M1_DDR_DQS_N0
C16
M1_DDR_DQS1
B14
M1_DDR_DQS_N1
A14
M1_DDR_DQS2
B7
M1_DDR_DQS_N2
C7
M1_DDR_DQS3
B5
M1_DDR_DQS_N3
A5
M1_DDR_DM0
A13
M1_DDR_DM1
A16
M1_DDR_DM2
A4
M1_DDR_DM3
A7
M1_DDR_DQ0
B18
M1_DDR_DQ1
B11
M1_DDR_DQ2
C19
M1_DDR_DQ3
C12
M1_DDR_DQ4
A19
M1_DDR_DQ5
A11
M1_DDR_DQ6
B19
M1_DDR_DQ7
C11
M1_DDR_DQ8
B12
M1_DDR_DQ9
B17
M1_DDR_DQ10
C13
M1_DDR_DQ11
C18
M1_DDR_DQ12
C14
M1_DDR_DQ13
A17
M1_DDR_DQ14
B13
M1_DDR_DQ15
C17
M1_DDR_DQ16
B9
M1_DDR_DQ17
C3
M1_DDR_DQ18
C10
M1_DDR_DQ19
B2
M1_DDR_DQ20
A10
M1_DDR_DQ21
A2
M1_DDR_DQ22
B10
M1_DDR_DQ23
C2
M1_DDR_DQ24
B3
M1_DDR_DQ25
B8
M1_DDR_DQ26
C4
M1_DDR_DQ27
C9
M1_DDR_DQ28
C5
M1_DDR_DQ29
A8
M1_DDR_DQ30
B4
M1_DDR_DQ31
C8
M1_RET
D5
M0_DDR_RESET_N
M1_DDR_RESET_N
R502
22
5%
H5TQ4G63AFR-RDC
IC500
H15_DDR_Hynix_29n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63AFR-RDC
IC502
H15_DDR_Hynix_29n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63AFR-RDC
IC501
H15_DDR_Hynix_29n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63AFR-RDC
IC503
H15_DDR_Hynix_29n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63CFR_RDC
IC500-*1
H15_DDR_Hynix_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63CFR_RDC
IC502-*1
H15_DDR_Hynix_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63CFR_RDC
IC501-*1
H15_DDR_Hynix_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ4G63CFR_RDC
IC503-*1
H15_DDR_Hynix_25n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
MAIN DDR
H5TQ1G63DFR-PBC(x16)
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
4Gbit : T7(A14)
DDR3 1.5V bypass Cap
- Place these caps near Memory
1Gbit : T7(NC_6)
Real USE : 1Gbit
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
2012-09-14
BSD-NC4_H005-HD
DDR3 1.5V bypass Cap
- Place these caps near Memory
Place M0 POWER PLANE
Place M1 POWER PLANE
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Содержание AUSYLJR
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