THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
EB_ADDR[9]
BOOT_MODE0
EB_DATA[0]
EB_DATA[1]
EB_ADDR[3]
EB_DATA[3]
EB_DATA[2]
EB_DATA[4]
EB_ADDR[2]
EB_ADDR[11]
EB_DATA[5]
EMMC_DATA[7]
EMMC_DATA[6]
EB_DATA[6]
EMMC_DATA[5]
EB_DATA[7]
EB_ADDR[12]
EB_ADDR[13]
EB_ADDR[6]
EMMC_DATA[0]
EB_ADDR[14]
EMMC_DATA[1]
EB_ADDR[0]
BOOT_MODE1
EMMC_DATA[2]
EB_ADDR[5]
EMMC_DATA[3]
EB_ADDR[7]
EMMC_DATA[4]
EB_ADDR[4]
EB_ADDR[1]
EB_ADDR[8]
EB_ADDR[10]
PLLSET1
R197
3.3K
+3.3V_NORMAL
I2C_SDA2
/PCM_CE2
R143
22
OPT
I2C_SDA5
+3.3V_NORMAL
/PCM_CE1
R133
10K
OPT
R180
3.3K
R168
10K
CI
I2C_SCL2
HW_OPT_7
R167
10K
CI
I2C_SDA4
CAM_IREQ_N
UART1_TX
R187
4.7K
R198
3.3K
I2C_SCL6
M_RFModule_ISP
BOOT_MODE1
HW_OPT_6
XO_MAIN
HW_OPT_0
HW_OPT_8
I2C_SDA2
CAM_CD2_N
RF_SWITCH_CTL
HW_OPT_2
R102
22
OPT
HW_OPT_4
R181
3.3K
FRC_RESET
/RST_HUB
TCK0
HW_OPT_1
UART1_RX
SOC_TX
CAM_REG_N
R196
3.3K
/USB_OCD3
R132
10K
OPT
I2C_SCL3
BOOT_MODE0
+3.3V_NORMAL
PLLSET0
TDI0
XIN_MAIN
CAM_CD1_N
C111
0.1uF
CAM_WAIT_N
UART1_RX
+3.3V_NORMAL
R166
10K
CI
R131
10K
OPT
ERROR_OUT
R103
22
OPT
R199
3.3K
I2C_SCL5
DSUB_DET
R150
22
+3.3V_NORMAL
I2C_SCL1
M_RFModule_RESET
CAM_INPACK_N
UART1_TX
R112
1M
R185
4.7K
OPT
SC_DET
TDO0
SOC_RX
TMS0
I2C_SCL5
I2C_SDA1
I2C_SCL4
M_REMOTE_TX
R186
4.7K
SOC_RESET
+3.3V_NORMAL
HW_OPT_3
R134
10K
OPT
R188
4.7K
OPT
HW_OPT_5
R142
22
OPT
I2C_SDA3
I2C_SDA6
/RST_PHY
TRST_N0
I2C_SCL2
I2C_SDA5
M_REMOTE_RX
COMP1_DET
HW_OPT_8
HW_OPT_1
R125
10K
UD
R138
10K
OPTIC
R100
10K
FRC_EXTERNAL
R139
10K
NON_OPTIC
R107
10K
FRC_INTERNAL
R140
10K
3D_DEPTH
R154
10K
DVB_S_TUNER
HW_OPT_2
R152
10K
DVB_T2_TUNER
R155
10K
NON_DVB_S_TUNER
HW_OPT_5
R153
10K
NON_DVB_T2_TUNER
HW_OPT_7
R141
10K
NON_3D DEPTH
HW_OPT_3
+3.3V_NORMAL
R146
10K
1GByte
R145
10K
OPT
R148
10K
NON_CP_BOX
R111
10K
FRC3
R124
10K
FHD
HW_OPT_4
R147
10K
CP_BOX
HW_OPT_6
R110
10K
URSA5
HW_OPT_0
HW_OPT_9
HW_OPT_9
R158
10K
NON_DVB_C2_TUNER
R156
10K
DVB_C2_TUNER
HP_DET
PCM_RST
/TU_RESET
/S2_RESET
I2C_BE_SDA1
I2C_SDA1
R151
22
R160
22
R162
22
I2C_BE_SCL1
FRC3_RESET
I2C_SCL1
FRC_RESET
LOCAL_DIM_EN
R170
10K
FRC3
SMARTCARD_RST
SMARTCARD_VCC
SMARTCARD_DET
SMARTCARD_DATA
SMARTCARD_CLK
SMARTCARD_PWR_SEL
SMARTCARD_DATA
SMARTCARD_PWR_SEL
SMARTCARD_DET
SMARTCARD_CLK
SMARTCARD_RST
SMARTCARD_VCC
I2C_SDA3
I2C_SCL3
HDMI_INT
HDMI_S/W_RESET
MHL_DET
SW1
JTP-1127WEM
DEBUG
1
2
4
3
Q100
2N7002K
S
D
G
Q103
2N7002K
S
D
G
+5V_NORMAL
Q104
2N7002K
S
D
G
Q105
2N7002K
OPT
S
D
G
+3.3V_NORMAL
R201
2.7K
1/16W
5%
C100
8pF
50V
C101
8pF
50V
+5V_NORMAL
R202
100K
R203
100K
OPT
R126
10K
NOT_ZORAN_FRC
R121
10K
ZORAN_FRC
HW_OPT_10
HW_OPT_10
+3.3V_NORMAL
PLLSET1
EMMC_DATA[0-7]
R176
22
OPT
EB_OE_N
WIFI_DP
BOOT_MODE0
USB_HUB_IC_IN_DM
EMMC_CLK
R174
22
OPT
WIFI_DM
USB_DP3
USB_CTL3
EMMC_CMD
EMMC_RST
EB_DATA[0-7]
DTV_ATV_SELECT
USB_DM3
USB_HUB_IC_IN_DP
AV1_CVBS_DET
EB_BE_N1
EB_BE_N0
BOOT_MODE1
EB_WE_N
EB_ADDR[0-14]
PLLSET0
R105
22
EPHY_RXD0
EPHY_REFCLK
R108
22
EPHY_TXD1
EPHY_EN
EPHY_CRS_DV
EPHY_TXD0
EPHY_MDIO
EPHY_RXD1
EPHY_MDC
R106
22
I2C_SCL3
I2C_SCL5
I2C_SDA4
I2C_SCL6
I2C_SCL4
I2C_SDA6
I2C_SDA3
I2C_SCL1
I2C_SDA1
I2C_SDA2
I2C_SDA5
I2C_SCL2
XIN_MAIN
XO_MAIN
R104
560
1%
TDO0
TDI0
TMS0
TCK0
TRST_N0
PCM_5V_CTL
+5V_NORMAL
+3.3V_NORMAL
+3.3V_NORMAL
3D_DEPTH_RESET
FLASH_WP
MO_SENS_TO_MAIN_DOWN
MO_SENS_TO_MAIN_UP
MOTOR_CLOSE_SW
MOTOR_OPEN_SW
MOTOR_CW
MOTOR_CCW
MOTOR_CLOSE_SW
MO_SENS_TO_MAIN_DOWN
MOTOR_CW
MOTOR_CCW
MO_SENS_TO_MAIN_UP
MOTOR_OPEN_SW
R109
10K
+3.3V_NORMAL
P100
12507WS-04L
DEBUG
1
2
3
4
5
R184
1.2K
R183
1.2K
OLED_TCON_RESET
OPTIC_FPGA_RESET
FPGA_LVDS_INFO
OPTIC_SERDES_RESET
OPTIC_SERDES_RESET
OPTIC_FPGA_RESET
OLED_TCON_RESET
EPHY_INT
3D_DEPTH_RESET
IRB_SPI_SS
IRB_SPI_CK
IRB_SPI_MOSI
IRB_SPI_MISO
IR_B_RESET
IRB_SPI_MISO
IRB_SPI_SS
IRB_SPI_CK
IRB_SPI_MOSI
IR_B_RESET
EPHY_INT
SEL_USB3
SEL_USB2
/RST_PHY
SEL_USB3
SC_DET
SEL_USB1
SEL_USB1
HP_DET
SEL_USB2
IC102
R1EX24256BSAS0A
3
A2
2
A1
4
VSS
1
A0
5
SDA
6
SCL
7
WP
8
VCC
/USB_OCD2
R101
22
HP_AMP_MUTE
R117
22
OPT
DiiVA_POD_CTL
DiiVA_POD_CTL
IC100
LG1152D-B1
LG1152_NON_RM
XIN_MAIN
A22
XO_MAIN
B22
OPM1
AB16
OPM0
AB17
PORES_N
AE3
TRST_N0
V23
TMS0
U25
TCK0
V25
TDI0
V24
TDO0
U24
TRST_N1
Y22
TMS1
AA22
TCK1
AB20
TDI1
AB21
TDO1
W22
PLLSET1
AB9
PLLSET0
AB8
BOOT_MODE1
AB15
BOOT_MODE0
AB14
EXT_INTR3/GPIO48
Y23
EXT_INTR2/GPIO63
W25
EXT_INTR1/GPIO62
W24
EXT_INTR0/GPIO61
W23
UART0_RX/GPIO49
Y5
UART0_TX/GPIO50
W6
UART1_RX
AA6
UART1_TX
Y6
UART2_RX
AB5
UART2_TX
AA5
SPI_DI0/GPIO39
AB23
SPI_DO0/GPIO38
AB24
SPI_SCLK0/GPIO37
AA25
SPI_CS0/GPIO36
AB25
SPI_DI1/GPIO35
Y25
SPI_DO1/GPIO34
AA23
SPI_SCLK1/GPIO33
Y24
SPI_CS1/GPIO32
AA24
SCL0/GPIO60
AB6
SDA0/GPIO59
AB4
SCL1/GPIO58
AC5
SDA1/GPIO57
AC4
SCL2/GPIO56
AD4
SDA2/GPIO71
AE4
SCL3/GPIO70
AE5
SDA3/GPIO69
AD5
SCL4/GPIO68
AE6
SDA4/GPIO67
AD6
SCL5/GPIO66
AC6
SDA5/GPIO65
AC7
RMII_REF_CLK
AD2
RMII_CRS_DV
AB1
RMII_MDIO
AB2
RMII_MDC
AB3
RMII_TXEN
AC2
RMII_TXD1
AC3
RMII_TXD0
AE1
RMII_RXD1
AD3
RMII_RXD0
AD1
CAM_CE1_N
W26
CAM_CE2_N
V28
CAM_CD1_N
Y27
CAM_CD2_N
Y26
CAM_VS1_N
W28
CAM_VS2_N
W27
CAM_IREQ_N
AA28
CAM_RESET
AB26
CAM_INPACK_N
AA27
CAM_VCCEN_N
AA26
CAM_WAIT_N
Y28
CAM_REG_N
V27
CAM_IOIS16_N
V26
SC_CLK/GPIO90
R25
SC_DETECT/GPIO93
U23
SC_VCCEN/GPIO89
T25
SC_VCC_SEL/GPIO88
T24
SC_RST/GPIO91
T23
SC_DATA/GPIO92
R24
SD_CLK/GPIO76
C22
SD_CMD/GPIO73
C23
SD_CD_N/GPIO75
A23
SD_WP_N/GPIO74
B23
SD_DATA3/GPIO72
A24
SD_DATA2/GPIO87
B24
SD_DATA1/GPIO86
C24
SD_DATA0/GPIO85
A25
USB_DP1
B27
USB_DM1
A27
USB_DP2
A26
USB_DM2
B26
USB_TXR_RKL
C25
USB_ANALOGTEST
B25
BT_USB_DP
AA1
BT_USB_DM
AA2
BT_TXR_RKL
AA4
BT_ANALOGTEST
Y4
EMMC_RST
E28
EMMC_CLK
F27
EMMC_CMD
F26
EMMC_DATA7
C26
EMMC_DATA6
E27
EMMC_DATA5
E26
EMMC_DATA4
D27
EMMC_DATA3
D28
EMMC_DATA2
C27
EMMC_DATA1
C28
EMMC_DATA0
D26
NAND_CS1
R23
NAND_CS0
P24
NAND_ALE
N25
NAND_CLE
P23
NAND_REN
N24
NAND_WEN
P25
GPIO31
AC1
GPIO30
V7
GPIO29
W5
GPIO28
W4
GPIO27
V6
GPIO26
V5
GPIO25
V4
GPIO24
U6
GPIO23
U5
GPIO22
U4
GPIO21
T6
GPIO20
T5
GPIO19
T4
GPIO18
R6
GPIO17
R5
GPIO16
R4
GPIO15
P6
GPIO14
P5
GPIO13
P4
GPIO12
N6
GPIO11
N5
GPIO10
N4
GPIO9
N3
GPIO8
M6
GPIO7
AC23
GPIO6
AC24
GPIO5
AE24
GPIO4
AD23
GPIO3
AE23
GPIO2
AC22
GPIO1
AD22
GPIO0
AE22
EB_CS3/GPIO64
M25
EB_CS2/GPIO79
M24
EB_CS1/GPIO78
M23
EB_CS0/GPIO77
N23
EB_OE_N
T27
EB_WE_N
T28
EB_WAIT
U27
EB_BE_N1
U26
EB_BE_N0
U28
EB_ADDR17/GPIO84
J22
EB_ADDR16/GPIO83
K22
EB_ADDR15/GPIO82
J23
EB_ADDR14
L26
EB_ADDR13
L27
EB_ADDR12
L25
EB_ADDR11
N26
EB_ADDR10
N27
EB_ADDR9
M26
EB_ADDR8
L28
EB_ADDR7
L24
EB_ADDR6
L23
EB_ADDR5
K28
EB_ADDR4
K27
EB_ADDR3
K26
EB_ADDR2
K25
EB_ADDR1
K24
EB_ADDR0
K23
EB_DATA15
V22
EB_DATA14
U22
EB_DATA13
T22
EB_DATA12
R22
EB_DATA11
P22
EB_DATA10
N22
EB_DATA9
M22
EB_DATA8
L22
EB_DATA7
T26
EB_DATA6
R28
EB_DATA5
R27
EB_DATA4
R26
EB_DATA3
P28
EB_DATA2
P27
EB_DATA1
P26
EB_DATA0
N28
R178
2.2K
R179
2.2K
R182
2.2K
R195
2.2K
R173
R175
X101
24MHz
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
FPGA_LVDS_INFO
D100
RCLAMP0502BA
OPT
SOC_RESET
R113
4.7K
IC100-*1
LG1152_RM
XIN_MAIN
A22
XO_MAIN
B22
OPM1
AB16
OPM0
AB17
PORES_N
AE3
TRST_N0
V23
TMS0
U25
TCK0
V25
TDI0
V24
TDO0
U24
TRST_N1
Y22
TMS1
AA22
TCK1
AB20
TDI1
AB21
TDO1
W22
PLLSET1
AB9
PLLSET0
AB8
BOOT_MODE1
AB15
BOOT_MODE0
AB14
EXT_INTR3/GPIO48
Y23
EXT_INTR2/GPIO63
W25
EXT_INTR1/GPIO62
W24
EXT_INTR0/GPIO61
W23
UART0_RX/GPIO49
Y5
UART0_TX/GPIO50
W6
UART1_RX
AA6
UART1_TX
Y6
UART2_RX
AB5
UART2_TX
AA5
SPI_DI0/GPIO39
AB23
SPI_DO0/GPIO38
AB24
SPI_SCLK0/GPIO37
AA25
SPI_CS0/GPIO36
AB25
SPI_DI1/GPIO35
Y25
SPI_DO1/GPIO34
AA23
SPI_SCLK1/GPIO33
Y24
SPI_CS1/GPIO32
AA24
SCL0/GPIO60
AB6
SDA0/GPIO59
AB4
SCL1/GPIO58
AC5
SDA1/GPIO57
AC4
SCL2/GPIO56
AD4
SDA2/GPIO71
AE4
SCL3/GPIO70
AE5
SDA3/GPIO69
AD5
SCL4/GPIO68
AE6
SDA4/GPIO67
AD6
SCL5/GPIO66
AC6
SDA5/GPIO65
AC7
RMII_REF_CLK
AD2
RMII_CRS_DV
AB1
RMII_MDIO
AB2
RMII_MDC
AB3
RMII_TXEN
AC2
RMII_TXD1
AC3
RMII_TXD0
AE1
RMII_RXD1
AD3
RMII_RXD0
AD1
CAM_CE1_N
W26
CAM_CE2_N
V28
CAM_CD1_N
Y27
CAM_CD2_N
Y26
CAM_VS1_N
W28
CAM_VS2_N
W27
CAM_IREQ_N
AA28
CAM_RESET
AB26
CAM_INPACK_N
AA27
CAM_VCCEN_N
AA26
CAM_WAIT_N
Y28
CAM_REG_N
V27
CAM_IOIS16_N
V26
SC_CLK/GPIO90
R25
SC_DETECT/GPIO93
U23
SC_VCCEN/GPIO89
T25
SC_VCC_SEL/GPIO88
T24
SC_RST/GPIO91
T23
SC_DATA/GPIO92
R24
SD_CLK/GPIO76
C22
SD_CMD/GPIO73
C23
SD_CD_N/GPIO75
A23
SD_WP_N/GPIO74
B23
SD_DATA3/GPIO72
A24
SD_DATA2/GPIO87
B24
SD_DATA1/GPIO86
C24
SD_DATA0/GPIO85
A25
USB_DP1
B27
USB_DM1
A27
USB_DP2
A26
USB_DM2
B26
USB_TXR_RKL
C25
USB_ANALOGTEST
B25
BT_USB_DP
AA1
BT_USB_DM
AA2
BT_TXR_RKL
AA4
BT_ANALOGTEST
Y4
EMMC_RST
E28
EMMC_CLK
F27
EMMC_CMD
F26
EMMC_DATA7
C26
EMMC_DATA6
E27
EMMC_DATA5
E26
EMMC_DATA4
D27
EMMC_DATA3
D28
EMMC_DATA2
C27
EMMC_DATA1
C28
EMMC_DATA0
D26
NAND_CS1
R23
NAND_CS0
P24
NAND_ALE
N25
NAND_CLE
P23
NAND_REN
N24
NAND_WEN
P25
GPIO31
AC1
GPIO30
V7
GPIO29
W5
GPIO28
W4
GPIO27
V6
GPIO26
V5
GPIO25
V4
GPIO24
U6
GPIO23
U5
GPIO22
U4
GPIO21
T6
GPIO20
T5
GPIO19
T4
GPIO18
R6
GPIO17
R5
GPIO16
R4
GPIO15
P6
GPIO14
P5
GPIO13
P4
GPIO12
N6
GPIO11
N5
GPIO10
N4
GPIO9
N3
GPIO8
M6
GPIO7
AC23
GPIO6
AC24
GPIO5
AE24
GPIO4
AD23
GPIO3
AE23
GPIO2
AC22
GPIO1
AD22
GPIO0
AE22
EB_CS3/GPIO64
M25
EB_CS2/GPIO79
M24
EB_CS1/GPIO78
M23
EB_CS0/GPIO77
N23
EB_OE_N
T27
EB_WE_N
T28
EB_WAIT
U27
EB_BE_N1
U26
EB_BE_N0
U28
EB_ADDR17/GPIO84
J22
EB_ADDR16/GPIO83
K22
EB_ADDR15/GPIO82
J23
EB_ADDR14
L26
EB_ADDR13
L27
EB_ADDR12
L25
EB_ADDR11
N26
EB_ADDR10
N27
EB_ADDR9
M26
EB_ADDR8
L28
EB_ADDR7
L24
EB_ADDR6
L23
EB_ADDR5
K28
EB_ADDR4
K27
EB_ADDR3
K26
EB_ADDR2
K25
EB_ADDR1
K24
EB_ADDR0
K23
EB_DATA15
V22
EB_DATA14
U22
EB_DATA13
T22
EB_DATA12
R22
EB_DATA11
P22
EB_DATA10
N22
EB_DATA9
M22
EB_DATA8
L22
EB_DATA7
T26
EB_DATA6
R28
EB_DATA5
R27
EB_DATA4
R26
EB_DATA3
P28
EB_DATA2
P27
EB_DATA1
P26
EB_DATA0
N28
MAIN & GPIO
1
A0’h
System Configuration
BOOT_MODE0
PLL SET[1:0] ==> Internal Pull-UP. N.C is high
00 : CPU clock(1056Mhz), Main0,1/2 DDR (792/792 Mhz)
01 : CPU clock(792Mhz), Main0,1/2 DDR (672/792 Mhz)
10 : CPU clock(1152Mhz), Main0,1/2 DDR (792/672 Mhz)
11 : CPU clock(984Mhz), Main0,1/2 DDR (792/792 Mhz)
I2C PULL UP
Write Protection
- Low : Normal Operation
- High : Write Protection
BOOT_MODE1
LG1152 B1
BOOT MODE
"11" or "01" : NOR
"10" : eMMC
"00" : NAND
NVRAM
Debug
MAIN Clock(24Mhz)
JTAG I/F FOR MAIN
Clock for LG1152
BackEnd 2
Pannel Resol
OPTIC I/F
FrontEnd 1
3D Depth IC
FrontEnd 2
CP BOX
BackEnd 1
DDR Size
Place to LVDS Wafer
For ISP
Delete PV
for DiiVA(China)
T2 Tuner
MODEL_OPT_1
MODEL_OPT_3
MODEL_OPT_9
MODEL_OPT_10
Enable
1
0
DDR
Reserved
MODEL OPTION 8 is just for CP Box
It should not be appiled at MP
NON_3D_Depth_IC
1
NON_OPTIC
Support
OPTIC
LOW
0
0
Not Support
MODEL_OPT_6
MODEL_OPT_0
Zoran FRC
DDR_Default
MODEL_OPT_4
LG FRC3
FHD
S Tuner
1
0
1
CP BOX
Support
HIGH
Not Support
3D DEPTH
SoC
internal
FRC
Disable
3D_Depth_IC
MODEL_OPT_7
NO_FRC
UD
MODEL_OPT_5
Support
Not Support
MODEL_OPT_8
MODEL_OPT_2
Not Support
URSA5
Support
C2 Tuner
(For UD)
Place near Jack side
Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Содержание 84LM9600
Страница 53: ......
