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Only training and service purposes.
K3Lp
CEDS/EPI
6Lane
68pin
HTPD
An_I
N
[GPI
O_5_VBY_LOCK/EPLOCK]
[GPI
O_4_VBY_HT
PD/T
CON_14]
BOE
Panel
3840x2160@60p
1.5Gbps
[E
PI
_T
X12~EPI
_T
X23]
HT
PD
A
IN
LOCK
An_I
N
CEDS/EPI
6Lane
68Pin
LGD
Panel
3840x2160@60p
3Gbps
PMIC
&
Le
ve
l Sh
ifter
SW50B3
A(
LGD)
SW5253(BOE)
CL
K(x10)
VCOM1
VCOMLFB
/ VCOMRFB
VCOM2 VGL1
VS
T
GIP
_RST
LS
_V
GL
VGH_EVEN
VGH_ODD
HVDD
EPI
3Lane
60
P
EPI
3Lane
60
P
HV
DD
HV
DD
GM
A
(1,
5,
6,
9,
10, 13,
24,18
)
[GPI
O_5_VBY_LOCK/EPLOCK]
PMIC_RESET
[GPI
O7_P
MI
C_RESE
T]
LOCKOUT12
GST,
E/O,
MC
LK,
GLCK
[GPI
O019_DA
C_OUT
]
[GPI
O_0_DA
C_SCLK]
[GPI
O_4_VBY_HT
PD/T
CON_14
]
[GPO_1_T
CON_
I2
C_EN/T
CON_2
]
Boost/Buck
(RT5043A)
VDD,
VCORE
SWG
SWO
SWI
[E
PI
_T
X12~EP
I_
TX
23
]
GA
MM
A
(RT6508) BOE Only
GM
A
(2,
3,
4,
7,
8,
11,
12, 15,
16,
17
)
[GPI
O_2_T
CON_SCL/T
CON_9
]
[GPI
O_1_T
CON_SD
A/
TCON_5]
68pi
n
60pin
68pin
60pin
3. EPI / CEDS Block Diagram
Содержание 55UJ634V
Страница 101: ......