- 22 -
LGE Internal Use Only
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
M
A
IN
A
ud
io
A
M
P
(N
TP
75
14
)
M
st
ar
L
M
14
C
I S
lo
t
P_
TS
P_
TS
T/
C
D
em
od
IF
(+
/-)
U
SB
1
O
PT
IC
LA
N
D
D
R
3
18
66
X
1
6
(5
12
M
B
X
2
EA
)
H
D
M
I1
(H
D
C
P2
.2
)
H
D
M
I2
(A
R
C
)
H
D
M
I3
(M
H
L)
A
na
lo
g
D
em
od
SY
ST
EM
E
EP
R
O
M
(2
56
K
b)
H
D
M
I
M
U
X
A
ir/
C
ab
le
TU
N
ER
(T
2/
C
/A
)
TU
N
ER
(S
2)
D
VB
-S
D
EM
O
D
(S
2)
LN
B
U
SB
2
U
SB
3
(2
.0
)
Vi
de
o
4K
@
30
p/2K@
60
p(
Vx
1
4
la
ne
),
O
SD
F
H
D
@
60
p(
Vx
1
2
la
ne
)
eM
M
C
(4
G
B
)
Su
b
M
ic
om
(R
EN
ES
A
S
R
5F
10
0G
EA
FB
)
D
D
R
3
1
86
6
X
16
(5
12
M
B
X
2
EA
)
P_
TS
X_
TA
L
24
M
H
z
T2
/C
/S
2
W
/O
A
D
A
B
X_
TA
L
32
.7
68
K
H
z
I2
S
O
ut
I2C
4
Vx
1
U
SB
P_
TS
I2C
1
H
/P
A
V/
C
O
M
P
SC
A
R
T
(IN
/O
U
T)
O
C
P
2A
O
C
P
1.
5A
(H
D
D
)
R E A R (H
)
C
VB
S/
YP
bP
r
C
VB
S/
R
G
B
SP
D
IF
O
U
T
ET
H
ER
N
ET
I2C
0
IR
/ KE
Y
W
IF
I/B
T
C
om
bo
LO
G
O
L
IG
H
T(
R
ea
dy
)
SU
B
A
SS
Y
IR
/K
EY
U
SB
_W
IF
I
C
VB
S
X_
TA
L
27
M
H
z
H
D
C
P2
.2
R
95
31
A
N
Se
ria
l
Fl
as
h(
4M
B)
Si
l9
61
7
LG
E7
41
1
Mux
LG
E7
41
1
BLOCK DIAGRAM
