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Copyright ©
LG Electronics Inc. All rights reserved.
Only for training and service purposes.
BLOCK DIAGRAM
1. Main IC
Main IC
eMMC (4GB
)
CI
S
lot
USB1 (2
.0
)
OC
P
USB2 (2
.0
)
HDMI
3
HDMI
2(ARC)
HDMI
1
Air/
Cabl
e
TUNE
R
(T2/C/
A)
TUNE
R
(S,S2)
DV
B-
S
LN
B
T2/C/S/S2 H
-NI
M tune
r
IF
(+
/-)
P_TS_O
UT
P_TS_I
N
Sub
MI
CO
M
X_
TA
L
32.768KHz
I2
C
1
IR
/ KEY
LOGO LIGHT(Ready)
WI
FI/BT
Co
mb
o
USB_WI
FI
X_
TA
L
24MHz
Sub Assy
LA
N
ETHERNET
SPDIF
AV/COMP
CVBS/YPbPr
SPDIF OU
T
H/P
AMP
RS-232
MAX323
MA
IN
A
udio
AM
P
I2S
Ou
t
I2
C
4
Vx
1 51P
(8 lane)
Vx
1 / EPI/ CEDS
FCIC
SPI/ I2C
6
EPI
PM
IC
Level
shifte
r
M0
M1
IF_S
IF
GST/
MCLK
/G
CL
K/EO/I2C
6
NVRAM
(256Kb
)
I2
C
4
I2
C
2
EPI
bloc
k
IQ
(+
/-),
IP(+/-
)
HDMI
4
TS
DDR3
2133
X
32
(256
MB
X
2EA)
DDR3
2133
X
32
(512
MB
X
2EA)
EPI
60P
(65”:8 lane,
55”
↓:6
lane),
CEDS 68
P
Area
OP
T