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Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes.
24MHz
xT
AL
CTOP_GF
x_
R1
0
GP
UP
LL
CO
RE
_P
LL
CTOP_FMC_R08/09/10
M0
M1
EM
MC
CO
RE
AU
D
ES
M
CTOP_GFx_R10[21] ck_mux_pl
l_sel_
m0
:
0:
DDR_M0PLL, 1:
DDR_M1PL
L
DD
R_
M1
PL
L
1308MHz(1056MHz)
200MHz
396MHz
552MHz
264MHz
DC
O
DI
SP
P
LL
C4
Tx
27 MH
z
594
MH
z
1/n
1/n
1/n
1/n
64
8 M
Hz
15
84
M
Hz
22
08
MH
z
CTOP_FME
0_R13/14/1
5
CODEC
PLL
20
16
MH
z
CP
U_
PL
L
CO
DE
C_
PL
L
24
00
MH
z
CP
UB
US
1308MHz(1056MHz)
528MHz
26
16
MH
z(2
11
2M
Hz
)
GF
x
600MHz
1/n
TE
GP
U
480MHz
648MHz
CTOP_GFx_R10[19] ck_mux_p
ll_sel_m
1
: 0:
DDR_M0PLL, 1:
DDR_M1PL
L
CTOP_GFx_R10[9:8]
ck_mux_pll_sel_
es
m
: 0:
CORE_PLL, 1:
CODEC_PLL, 2:DDR_M1
PL
L
CTOP_GFx_R10[17:16]
ck_mux_pll_se
l_lbus
:
0:
CORE_PLL, 1:
CODEC_PLL
, 2:DDR_M1PL
L
[27:26]
ck_mux_pll_sel_
dc
o
: 0:
CODEC_PLL, 1:
CORE_PLL, 2:
DDR_M1PL
L
CTOP_GFx_R16/17/18
CTOP_GFx_R00/01/02
CTOP_DPE_R28,29,30
CTOP_GFx_R06/07/08
CTOP_GFx_R10[31:30]
ck_mux_pll_se
l_co
re
:
0:
CORE_PLL, 1:
CODEC_PLL, 2:DDR_M1
PL
L
CTOP_GFx_R10[2:1]
ck_mux_pll_sel_em
mc
:
0:
CODEC_PLL, 1:
CORE_PLL
, 2:DDR_M1PL
L
CTOP_GFx_R10[15:14]
ck_mux_pll_se
l_emmc
:
0:
CODEC_PLL, 1:
CORE_PLL
, 2:DDR_M1PL
L
1/n
CP
U
CTOP_GFx_R03/04/05
DD
R_
M0
PL
L
1/ 2
1/ 2
1/ 2
AU
D
8. Clock source and frequency inside chip
Содержание 43UJ750 -ZB Series
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