LG 43UF67 Series, Руководство по обслуживанию

Страница: 38 / 83

GPIO (RESERVED FOR U11)
U11 ONLY, NC FOR U11P
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
URSA_RESET
XIN_URSA
XO_URSA
SCL2_+3.3V_URSA
AR1351
33
SDA2_+3.3V_URSA
R13568 1M
C1351 8pF 50V
X1351 24MHz
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
XIN_URSA
C1352 8pF 50V
XO_URSA
D1351
100V
1N4148W
OPT
+3.3V_U_NORMAL
R13578
0
R13572
470K
OPT
URSA_RESET_SoC
R13577
10K
C1354
1uF
10V
OPT
+3.3V_U_NORMAL
URSA_RESET
R13571 33
URSA_DEBUG
URSA_SCL
SDA2_+3.3V_URSA
R13574
0
URSA_MP
R13584
0
OPT
SCL2_+3.3V_DB
P1351
12507WS-04L
WAFER-STRAIGHT
URSA_DEBUG
1
2
3
4
5
URSA_SDA
R13575
0
OPT
R13570 33
URSA_DEBUG
SDA2_+3.3V_DB
SW1352
JS2235S
URSA_DEBUG
3
2
1
4
5
6
SCL2_+3.3V_URSA
SCL2_+3.3V_DB
SDA2_+3.3V_DB
R13583
0
URSA_MP
P1352
12507WS-04L
URSA11_PQ_DEBUG
1
2
3
4
5 C1356
0.1uF
16V
URSA11_PQ_DEBUG
R13576
10K
URSA11_PQ_DEBUG
R13582
33
URSA11_PQ_DEBUG
+3.3V_U_NORMAL
R13579
33
URSA11_PQ_DEBUG
URSA_UART2_TX
URSA_UART2_RX
URSA_UART2_TX
URSA_UART2_RX
URSA_UART1_TX
URSA_UART1_RX
+3.3V_U_NORMAL
P1353
12507WS-04L
URSA11_SYS_DEBUG
1
2
3
4
5
R13581
33
URSA11_SYS_DEBUG
R13580
33
URSA11_SYS_DEBUG
R13573
10K
URSA11_SYS_DEBUG
C1355
0.1uF
16V
URSA11_SYS_DEBUG
URSA_UART1_RX
URSA_UART1_TX
SPI_CZ
SPI_DO
AR1352
33
SPI_DI
SPI_CK
FLASH_WP_URSA
SPI_DO
FRC_FLASH_WP
R13558 1K
OPT
IC1351
MX25L3235E
URSA_FLASH_MX(MULTI)
3
WP/SIO2
2
SO/SIO1
4
GND
1
CS
5
SI/SIO0
6
SCLK
7
HOLD/SIO3
8
VCC
R13559 33
R13564
10K
OPT
SPI_CZ
IC1351-*1
W25Q32FVSSIG
URSA_FLASH_WINDBOND(MULTI)
3
WP[IO2]
2
DO[IO1]
4
GND
1
CS
5
DI[IO0]
6
CLK
7
HOLD_OR_RESET[IO3]
8
VCC
+3.3V_U_NORMAL
R13569 10K
C1353
0.1uF
16V
R13562
1K
SPI_DI
SPI_CK
R13518 0
R13519 0
URSA_L/D_CK
URSA_OPT_4
URSA_OPT_0
Div_BIT0
Div_BIT1
URSA_L/D_DI
URSA_L/D_VSYNC
DIM2
DIM0
DIM1
URSA_BIT1
URSA_BIT2
URSA_BIT0
R13540
10K
OPT
+3.3V_U_NORMAL
R13541
10K
DDC_SDA_HDMI1
DDC_SCL_HDMI1
Data_Format_0
DDC_SDA_HDMI2
DDC_SCL_HDMI2
Data_Format_1
R13524 33
R13525 33
FLASH_WP_URSA
R13543 10K
URSA_RX_Vx1_HTPDn
R13542 10K
URSA_RX_Vx1_HTPDn
DIM0
R13563
10K
DIM2
+3.3V_U_NORMAL
DIM1
R13567
10K
OPT
R13566
10K OPT
R13561
10K
R13560
10K
R13565
10K OPT
URSA_OPT_6
Div_BIT1
R13526
10K
OPT
R13554
10K
R13533
10K
Debug
R13550
10K
OPT
R13551
10K
R13536
10K
Div_BIT1_1
URSA_BIT2
Div_BIT0
R13527
10K
R13530
10K
OPT
R13544
10K
R13537
10K
Div_BIT1_0
URSA_OPT_4
R13545
10K
OPT
R13534
10K
Div_BIT0_1
URSA_BIT0
R13549
10K
URSA_BIT0_0
R13535
10K
Div_BIT0_0
R13553
10K
OPT
R13548
10K
URSA_BIT0_1
URSA_OPT_5
R13546
10K
OS_Module R13531
10K
URSA_OPT_1
URSA_OPT_0
R13547
10K
LGD_Module
R13532
10K
Release
+3.3V_U_NORMAL
URSA_BIT1
R13504 33
OPT
R13505 33
OPT
R13509 33
OPT
R13510 33
OPT
R13511 33
OPT
R13512 33
OPT
R13513 33
OPT
R13514 33
OPT
R13515 33
OPT
R13516 33
OPT
HTPDAn
R13557
10K
URSA_TX_HTPD_pulldown
R13556 220
R13552
10K
OPT
LOCKAn
Q1351
2N3906S-RTK
PNP_KEC(MULTI)
E
B
C
Q1351-*1
MMBT3906(NXP)
PNP_NXP(MULTI)
E
B
C
+3.3V_U_NORMAL
R13555
22
L
D
1
3
5
1
S
M
L
-
5
1
2
U
W
URSA_OPT_1
R13586
100K
R13585
100K
VID0
VID1
R13506
0
OPT
URSA_RESET_READY
SW1351
1 2
4 3
R13517 0
R13503 0
OPT
5V_DET_HDMI_2
5V_DET_HDMI_1
R13501 0
IC119
LGE5352(URSA11)
PAD_RESET
AD26
PAD_XOUT
AH4
PAD_XIN
AH3
PAD_I2C_S_SDA
AE9
PAD_I2C_S_SCL
AD9
PAD_I2C_M_SDA
AD10
PAD_I2C_M_SCL/[VSYNC_LIKE_SP1]
AE10
PAD_GPIO00/[UART2_TX]
E8
PAD_GPIO01/[UART2_RX]
F7
PAD_GPIO02/[UART1_TX]
E7
PAD_GPIO03/[CHIP_VDET]
F6
PAD_SPI_CZ
AD27
PAD_SPI_CK
AC27
PAD_SPI_DI
AC28
PAD_SPI_DO
AC26
PAD_INTERUPT_R21
AE25
PAD_INTERUPT_R20
AD25
PAD_IRE/[UART1_RX]
D7
PAD_TESTPIN
AC25
GND_EFUSE
AC9
GPIO[09]
AC19
GPIO[08]
AD19
GPIO[07]
AC18
GPIO[06]
AE19
GPIO[64]
AD7
GPIO[65]
AE7
GPIO[66]
AC7
GPIO[67]
AD8
GPIO[63]
AC8
GPIO[70]
M4
GPIO[72]
M5
GPIO[73]
N4
GPIO[71]
N5
NC_1
AE6
NC_2
AD6
PAD_I2C_HSC_SDA/[VSYNC_LIKE_SPI2]
AD11
PAD_I2C_HSC_SCL/[VSYNC_LIKE_SPI3]
AC10
PAD_SPI1_CK/GPIO58
AC23
PAD_SPI1_DI/GPIO59
AD24
PAD_SPI2_CK/GPIO56
AD23
PAD_SPI2_DI/GPIO57
AC22
PAD_SPI3_CK/GPIO54
AE24
PAD_SPI3_DI/GPIO55
AE22
PAD_SPI4_CK/GPIO52
AD22
PAD_SPI4_DI/GPIO53
AC21
PAD_VSYNC_LIKE/GPIO40
AC24
PAD_DIM00/GPIO32
AE13
PAD_DIM01/GPIO33
AD13
PAD_DIM02/GPIO34
AC13
PAD_DIM03/GPIO35
AE15
PAD_DIM04/GPIO36
AC14
PAD_DIM05/GPIO37
AD14
PAD_DIM06/GPIO38
AD15
PAD_DIM07/GPIO39
AC15
PAD_TCON0/STV2
E4
PAD_TCON1/OE
D5
PAD_TCON2/YV1C
E6
PAD_TCON3/CPV
E5
PAD_TCON4/STV1
F5
PAD_TCON5/SFT
F4
PAD_TCON6/TPV
D6
PAD_TCON7/POL
D4
PAD_TCON8/[VX1T_HTPDN]
AC4
PAD_TCON9/[VX1T_LOCKN]
AD4
PAD_TCON10/[HDMI_R_DDC_CLK3]
AA4
PAD_TCON11/[HDMI_R_DDC_DAT3]
AB5
PAD_TCON12/[HDMI_R_HP3]
AB4
PAD_TCON13/[HDMI_R_CEC3]
AA5
PAD_TCON14/[HDMI_T_CEC]
AD5
PAD_TCON15/[HDMI_T_HPD]
AE5
PAD_GPIO04
AD21
PAD_GPIO05
AD20
GPIO[74]
AC6
GPIO[75]
AC5
GPIO[76]
AB7
GPIO[69]
AB6
PAD_GPIO10
AE21
PAD_GPIO11
AC20
PAD_GPIO12/[VX1_RX_HTPD_O]
AE12
PAD_GPIO13/[VX1_RX_HTPD_V]
AD12
PAD_GPIO14
AD18
PAD_GPIO15/[VX1_RX_LOCK_O]
AC11
PAD_GPIO16/[VX1_RX_LOCK_V]
AC12
PAD_GPIO17
AE18
NC_3
B1
NC_4
AG1
NC_5
AH2
NC_6
AH27
NC_7
B28
NC_8
AG28
URSA_OPT_6
URSA_OPT_5
URSA_BIT3
R13502
10K
OPT
R13507
10K
OPT
URSA_BIT3
R13523 0
R13522 0
R13520 0
R13521 0
132
U_UART_GPITO
2014.
URSA11P
Clock for URSA11
URSA Reset
Debugging for URSA
I2C_S Port
SPI Flash
Slave (Debug Port:0XB4,ISP:0X98)
CHIP_CONF:{DIM2,DIM1,DIM0}
Debug/ISP ADDR
CHIP_CONF=3’d7:111:boot from SPI Flash
Chip Config
URSA_BIT2_0
0/1/1
0/0/1
1/1
OLED 4K (4DDR)
Rx Interface
Tx Lane
Module Division
URSA_RX_LVDS
5k@120 (4DDR)
BIT [2/1/0]
Non Division
Division Type
URSA_BIT1_0
2 Division
4k@60 (2DDR)
1/0/0
0/1/0
URSA_RX_Vx1
URSA Option
0/1
4K@120 (4DDR)
URSA_BIT1_1
0/0
FHD@120 (4DDR)
FHD@60 (2DDR)
FHD@60 (4DDR) 1/1/0
BIT [1/0]
4 Division
0/0/0
URSA_BIT2_1
8 Division
4K@60Hz (4DDR)
1/0/1
1/0
1/1/1
* URSA_BIT3 : READY
Copyright © 2015 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only