GPIO (RESERVED FOR U11)
U11 ONLY, NC FOR U11P
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
R13206
33
OPT
C13207
8pF
50V
I2CS_SDA
R13202
33
OPT
Div_BIT0
DIM0
SPI_DI
SPI_CK
URSA_RESET_MICOM
URSA_UART2_RX
R13209
33
OPT
R13200 10K
OPT
R13264
10K
OPT
URSA_UART2_TX
R13261
0
URSA_MP
R13228
33
URSA_L/D_ctrl
+3.3V_NORMAL
I2C_SDA7
URSA_UART1_RX
R13241
22
URSA_OPT_6
L/D_VSYNC
Data_Format_0
XO_URSA
R13217
10K
URSA_OPT_5_0
R13249
10K
C13204
0.01uF
25V
R13243
10K
R13201 10K
OPT
R 13256 33
URSA_DEBUG
R13236
10K
URSA_BIT1_1
C13208
8pF
50V
R13213
10K
URSA_OPT_6_1
DIM1
FLASH_WP_URSA
DIM0
XO_URSA
R13219
10K
URSA_RX_Vx1_HTPDn
R13210
33
OPT
URSA_UART1_RX
SCL2_+3.3V_DB
SPI_CZ
Data_Format_1
URSA_UART2_RX
SDA2_+3.3V_DB
DIM2
Div_BIT1
URSA_RESET
C13217
0.01uF
25V
OPT
DIM2
C13215
5pF
50V
R13255
10K
L/D_DI
I2CS_SCL
R13225
10K
Div_BIT1_0
+3.3V_NORMAL
URSA_RESET_SoC
C13212
0.1uF
16V
URSA_PQ_DEBUG
Div_BIT0
LOCKAn
R13248
1K
U_SPI_WP_f_SoC
R13229
33
URSA_L/D_ctrl
AR13200
33
P13201
12507WS-04L
URSA_PQ_DEBUG
1
2
3
4
5
R13265
0
C13201
56pF
50V
OPT
R13268
33
URSA_PQ_DEBUG
URSA_UART2_TX
R13254
1M
SW13200
1
2
4
3
R13230
10K
URSA_OPT_0_1
XIN_URSA
R13262
0
OPT
R13246
10K
URSA_OPT_4
R13250
10K
OPT
C13216
5pF
50V
URSA_OPT_1
R13253
10K
OPT
VID0
C13218
0.01uF
25V
OPT
C13205
0.01uF
25V
+3.3V_NORMAL
URSA_OPT_6
Q13200
MMBT3906(NXP)
NXP_LOCKAN_LED_TR
E
B
C
+3.3V_NORMAL
R13224
10K
Div_BIT1_1
FLASH_WP_URSA
R13259
0
+3.3V_NORMAL
+3.3V_NORMAL
R13227
10K
C13214
5pF
50V
R13271
0
OPT
R13231
10K
URSA_OPT_0_0
SPI_DI
I2C_SCL7
LOCKAn_OSD
L
D
1
3
2
0
0
S
M
L
-
5
1
2
U
W
DIM1
URSA_BIT0
R13204
33
OPT
URSA_RESET
URSA_OPT_0
C13202
0.01uF
25V
C13211
0.1uF
16V
URSA_SYS_DEBUG
R13239
10K
URSA_BIT2_1
URSA_BIT1
R13223
10K
Div_BIT0_0
R13221
10K
URSA_OPT_4_0
R13237
10K
URSA_BIT1_0
HTPDAn
R13215
33
URSA_L/D_ctrl
URSA_BIT1
R13269
33
URSA_PQ_DEBUG
C13219
0.01uF
25V
OPT
LOCKAn_Video
URSA_OPT_4
R 13257 33
URSA_DEBUG
R13245
33
R13244
1K
U_SPI_WP_f_URSA
+3.3V_NORMAL
R13208
33
OPT
VID1
R13266
33
URSA_SYS_DEBUG
SPI_CZ
I2CS_SCL
R13212
0
SPI_DO
R13216
10K
URSA_OPT_5_1
Div_BIT1
C13200
56pF
50V
OPT
R13233
10K
URSA_OPT_1_1
P13202
12507WS-04L
URSA_SYS_DEBUG
1
2
3
4
5
C13206
0.01uF
25V
R13218
10K
URSA_RX_Vx1_HTPDn
I2CS_SDA
R13267
33
URSA_SYS_DEBUG
R13247
10K
R13252
10K
OPT
R13207
33
OPT
URSA_UART1_TX
C13209
0.1uF
16V
R13270
0
URSA_MP
XIN_URSA
R13226
10K
OPT
X13200
24MHz
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
+3.3V_NORMAL
P13200
12507WS-04L
WAFER-STRAIGHT
URSA_DEBUG
1
2
3
4
5
R13251
10K
OPT
SPI_CK
R13258
470K
OPT
URSA_UART1_TX
IC13200
MX25L3235E
URSA11_SERIAL_FLASH_MEMORY_MXIC(MAIN)
EAN62459501
MACRONIX INTERNATIONAL CO., LTD.
3
WP/SIO2
2
SO/SIO1
4
GND
1
CS
5
SI/SIO0
6
SCLK
7
HOLD/SIO3
8
VCC
+3.3V_NORMAL
C13220
0.01uF
25V
OPT
C13203
0.01uF
25V
R13232
10K
URSA_OPT_1_0
R13238
10K
R13222
10K
Div_BIT0_1
R13234
10K
URSA_BIT0_1
URSA_BIT2
SDA2_+3.3V_DB
R13260
10K
URSA_SYS_DEBUG
URSA_OPT_5
URSA_OPT_0
SPI_DO
R13235
10K
URSA_BIT0_0
C13213
0.01uF
25V
R13205
33
OPT
R13240
10K
URSA_BIT2_0
URSA_OPT_5
URSA_BIT2
L/D_CLK
R13220
10K
URSA_OPT_4_1
SCL2_+3.3V_DB
URSA9_CONNECT
R13203
33
OPT
R13263
10K
URSA_PQ_DEBUG
C13210
1uF
10V
OPT
SW13201
JS2235S
URSA_DEBUG
3
2
1
4
5
6
IC12800
LGE5352(URSA11)
PAD_RESET
AD26
PAD_XOUT
AH4
PAD_XIN
AH3
PAD_I2C_S_SDA
AE9
PAD_I2C_S_SCL
AD9
PAD_I2C_M_SDA
AD10
PAD_I2C_M_SCL/[VSYNC_LIKE_SP1]
AE10
PAD_GPIO00/[UART2_TX]
E8
PAD_GPIO01/[UART2_RX]
F7
PAD_GPIO02/[UART1_TX]
E7
PAD_GPIO03/[CHIP_VDET]
F6
PAD_SPI_CZ
AD27
PAD_SPI_CK
AC27
PAD_SPI_DI
AC28
PAD_SPI_DO
AC26
PAD_INTERUPT_R21
AE25
PAD_INTERUPT_R20
AD25
PAD_IRE/[UART1_RX]
D7
PAD_TESTPIN
AC25
GND_EFUSE
AC9
GPIO[09]
AC19
GPIO[08]
AD19
GPIO[07]
AC18
GPIO[06]
AE19
GPIO[64]
AD7
GPIO[65]
AE7
GPIO[66]
AC7
GPIO[67]
AD8
GPIO[63]
AC8
GPIO[70]
M4
GPIO[72]
M5
GPIO[73]
N4
GPIO[71]
N5
NC_1
AE6
NC_2
AD6
PAD_I2C_HSC_SDA/[VSYNC_LIKE_SPI2]
AD11
PAD_I2C_HSC_SCL/[VSYNC_LIKE_SPI3]
AC10
PAD_SPI1_CK/GPIO58
AC23
PAD_SPI1_DI/GPIO59
AD24
PAD_SPI2_CK/GPIO56
AD23
PAD_SPI2_DI/GPIO57
AC22
PAD_SPI3_CK/GPIO54
AE24
PAD_SPI3_DI/GPIO55
AE22
PAD_SPI4_CK/GPIO52
AD22
PAD_SPI4_DI/GPIO53
AC21
PAD_VSYNC_LIKE/GPIO40
AC24
PAD_DIM00/GPIO32
AE13
PAD_DIM01/GPIO33
AD13
PAD_DIM02/GPIO34
AC13
PAD_DIM03/GPIO35
AE15
PAD_DIM04/GPIO36
AC14
PAD_DIM05/GPIO37
AD14
PAD_DIM06/GPIO38
AD15
PAD_DIM07/GPIO39
AC15
PAD_TCON0/STV2
E4
PAD_TCON1/OE
D5
PAD_TCON2/YV1C
E6
PAD_TCON3/CPV
E5
PAD_TCON4/STV1
F5
PAD_TCON5/SFT
F4
PAD_TCON6/TPV
D6
PAD_TCON7/POL
D4
PAD_TCON8/[VX1T_HTPDN]
AC4
PAD_TCON9/[VX1T_LOCKN]
AD4
PAD_TCON10/[HDMI_R_DDC_CLK3]
AA4
PAD_TCON11/[HDMI_R_DDC_DAT3]
AB5
PAD_TCON12/[HDMI_R_HP3]
AB4
PAD_TCON13/[HDMI_R_CEC3]
AA5
PAD_TCON14/[HDMI_T_CEC]
AD5
PAD_TCON15/[HDMI_T_HPD]
AE5
PAD_GPIO04
AD21
PAD_GPIO05
AD20
GPIO[74]
AC6
GPIO[75]
AC5
GPIO[76]
AB7
GPIO[69]
AB6
PAD_GPIO10
AE21
PAD_GPIO11
AC20
PAD_GPIO12/[VX1_RX_HTPD_O]
AE12
PAD_GPIO13/[VX1_RX_HTPD_V]
AD12
PAD_GPIO14
AD18
PAD_GPIO15/[VX1_RX_LOCK_O]
AC11
PAD_GPIO16/[VX1_RX_LOCK_V]
AC12
PAD_GPIO17
AE18
NC_3
B1
NC_4
AG1
NC_5
AH2
NC_6
AH27
NC_7
B28
NC_8
AG28
URSA_OPT_1
R13211
0
R13214
10K
URSA_OPT_6_0
URSA_BIT0
D13200
100V
1N4148W
OPT
FRC_FLASH_WP
R14400
10K
OPT
+3.3V_NORMAL
R14401
10K
U_SPI_WP_f_SoC
R
1
3
2
4
2
1
0
K
Q13200-*1
2N3906S-RTK
KEC_LOCKAN_LED_TR
E
B
C
R14402
33
R14403
33
IC13200-*1
W25Q32FVSSIG
EAN62459301
URSA11_SERIAL_FLASH_MEMORY_WINBOND(SUB)
WINBOND ELECTRONICS CORP.
3
WP[IO2]
2
DO[IO1]
4
GND
1
CS
5
DI[IO0]
6
CLK
7
HOLD_OR_RESET[IO3]
8
VCC
URSA11_GPIO
CHIP_CONF:{DIM2,DIM1,DIM0}
SPI Flash
1/1/1
Reserved
4K@60(4 DDR)
1/1
0/0
Reserverd
FHD@60 (2 DDR)
OLED 4K@120(4 DDR)
2 Division
I2C_S Port
Chip Config
Reserved
BIT [2/1/0]
URSA_OPT_6
High
OS_Moudule
URSA Reset
URSA_OPT_5
Tx Lane
FHD@120 (4 DDR)
LGD_Module
4K@120 8K(98UF8K 4DDR)
CHIP_CONF=3’d7:111:boot from SPI Flash
LGD_Module
URSA_RX_LVDS
1/0
Low
FHD@60 (4 DDR)
4k@60 (2 DDR)
PRINT_OFF
1/1/0
URSA_OPT_0
Reserverd
4 Division
Tx Lane
Reserverd
0/1/1
0/0/1
Debugging for URSA11
URSA_RX_Vx1
Module Division
Rx_LVDS
Division Type
BIT [1/0]
PRINT_ON
Slave (Debug Port:0XB4,ISP:0X98)
1/0/1
Reserverd
8 Division
Debug/ISP ADDR
Clock for URSA11
URSA_OPT_4
Rx_Vx1
Non Division
4K@120 (4 DDR)
0/1
URSA_OPT_1
URSA Option
Module Type
Reserved
1/0/0
OS_Module
0/1/0
Rx Interface
0/0/0
BSD-15Y-LM14A-144_00-HD
Copyright © 2015 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Содержание 43UF640 -ZA Series
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