LG 42PX3DLV, Руководство по обслуживанию

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ADJUSTMENT INSTRUCTIONS
5. POWER PCB Assy Voltage
Adjustment
(Va, Vs Voltage Adjustment)
5-1. Test Equipment :
D.M.M 1EA
5-2. Connection Diagram for Measuring
Refer to Fig 1.
5-3. Adjustment
(1) Va Adjustment
1) C terminal of D.M.M to Va pin of P807 and
connect – terminal to GND pin of P807.
2) Adjust RV501 voltage to match that of the label on the
Top/Right of the panel. (Deviation : ±0.5V)
(2) Vs Adjustment
1) C terminal of D.M.M to Vs pin of P807 and
connect – terminal to GND pin of P807.
2) Adjust RV401 voltage to match that of the label on the
Top/Right of the panel. (Deviation : ±0.5V)
6. EDID(The Extended Display
Identification Data)/DDC
(Display Data Channel) download
This is the function that enables “Plug and Play".
6-1. EDID DATA for DVI
:
EDID for DVI (DDC (Display Data Channel) Data)
Block(0) EDID table =
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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00 | 00 FF FF FF FF FF FF 00 1E 6D 01 01 01 01 01 01
10 | 06 0E 01 03 98 5C 34 96 08 CF 72 A3 57 4C B0 23
20 | 09 45 5D EF CE 00 31 D9 31 59 45 59 01 01 01 01
30 | 01 01 01 01 01 40 C3 1E 00 20 41 00 20 30 10 60
40 | 13 00 98 08 32 00 00 18 00 00 00 FC 00 4C 47 20
50 | 54 56 0A 00 00 00 00 00 00 00 00 00 00 FD 00 30
60 | 4C 1E 64 0F 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 0A 00 00 00 00 00 00 00 00 00 00 00 00 01 1D
Block(1) EDID table =
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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00 | 02 01 04 00 01 1D 00 72 51 D0 1E 20 6E 28 55
00
10 | C4 8E 21 00 00 1E 8C 0A D0 8A 20 E0 2D 10 10
3E 20 | 96 00 C4 8E 21 00 00 18 01 1D 80 18 71 1C
16 20 30 | 58 2C 25 00 C4 8E 21 00 00 9E 00 00 00
00 00 00 40 | 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00
50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00
60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00
70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
BF
6-2. EDID DATA for RGB
:
EDID table =
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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00 | 00 FF FF FF FF FF FF 00 1E 6D 01 01 01 01 01 01
10 | 06 0E 01 03 18 5C 34 96 08 CF 72 A3 57 4C B0 23
20 | 09 45 5D EF CE 00 31 D9 31 59 45 59 01 01 01 01
30 | 01 01 01 01 01 40 C3 1E 00 20 41 00 20 30 10 60
40 | 13 00 98 08 32 00 00 18 00 00 00 FC 00 4C 47 20
50 | 54 56 0A 00 00 00 00 00 00 00 00 00 00 FD 00 30
60 | 4C 1E 64 0F 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 9E
Each PCB Assy must be checked by Check JIG Set before
assembly. (Especially, be careful Power PCB Assy which can
cause Damage to the PDP Module.)
<Fig. 1> Connection Diagram of Power Adjustment for the
Measuring (P/N: 6709V00010A)