THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
DDRS_ADDR[0]
DDRS_ADDR[1]
DDRS_ADDR[2]
DDRS_ADDR[3]
DDRS_ADDR[4]
DDRS_ADDR[5]
DDRS_ADDR[6]
DDRS_ADDR[7]
DDRS_ADDR[8]
DDRS_ADDR[9]
DDRS_ADDR[10]
DDRS_ADDR[11]
DDRS_DATA[0]
DDRS_DATA[1]
DDRS_DATA[2]
DDRS_DATA[3]
DDRS_DATA[4]
DDRS_DATA[5]
DDRS_DATA[6]
DDRS_DATA[7]
DDRS_DATA[8]
DDRS_DATA[9]
DDRS_DATA[10]
DDRS_DATA[11]
DDRS_DATA[12]
DDRS_DATA[13]
DDRS_DATA[14]
DDRS_DATA[15]
DDRS_DATA[16]
DDRS_DATA[17]
DDRS_DATA[18]
DDRS_DATA[19]
DDRS_DATA[20]
DDRS_DATA[21]
DDRS_DATA[22]
DDRS_DATA[23]
DDRS_DATA[24]
DDRS_DATA[25]
DDRS_DATA[26]
DDRS_DATA[27]
DDRS_DATA[28]
DDRS_DATA[29]
DDRS_DATA[30]
DDRS_DATA[31]
DDR_ADDR[12]
DDRS_ADDR[12]
DDR_ADDR[0]
DDR_ADDR[1]
DDR_ADDR[2]
DDR_ADDR[3]
DDR_ADDR[4]
DDR_ADDR[5]
DDR_ADDR[6]
DDR_ADDR[7]
DDR_ADDR[8]
DDR_ADDR[9]
DDR_ADDR[10]
DDR_ADDR[11]
DDR_DATA[0]
DDR_DATA[1]
DDR_DATA[2]
DDR_DATA[3]
DDR_DATA[4]
DDR_DATA[5]
DDR_DATA[6]
DDR_DATA[7]
DDR_DATA[8]
DDR_DATA[9]
DDR_DATA[10]
DDR_DATA[11]
DDR_DATA[12]
DDR_DATA[13]
DDR_DATA[14]
DDR_DATA[15]
DDR_DATA[16]
DDR_DATA[17]
DDR_DATA[18]
DDR_DATA[19]
DDR_DATA[20]
DDR_DATA[21]
DDR_DATA[22]
DDR_DATA[23]
DDR_DATA[24]
DDR_DATA[25]
DDR_DATA[26]
DDR_DATA[27]
DDR_DATA[28]
DDR_DATA[29]
DDR_DATA[30]
DDR_DATA[31]
+2.5LVDS_RX
+1.8V_DDRS
+3.3V_IO
+1.8V_DDR
+1.0VPLL
+2.5VPLL
+2.5LVDS_TX
+1.0VDC
DDRS_ADDR[0-12]
002:E16;002:W13;002:AK17;002:BD12
DDR_ADDR[0-12]
002:E39;002:W39;002:AH39;002:BD39
DDR_DATA[0-31]
002:N40;002:AQ40
DDRS_DATA[0-31]
002:N17;002:AT17
LVRX1_CLKP
008:V20
LVRX1_CLKM
008:V20
LVRX1_AP
008:V22
LVRX1_AM
008:V22
LVRX1_BP
008:V21
LVRX1_BM
008:V22
LVRX1_CP
008:V21
LVRX1_CM
008:V21
LVRX1_DP
008:V19
LVRX1_DM
008:V19
LVRX1_EP
008:V18
LVRX1_EM
008:V19
LVTX2_B-
009:O5
LVTX4_A-
009:E10
LVTX1_D-
009:O6
LVTX1_A-
009:O11
LVTX3_CLK-
009:E20
009:E17
009:O6
LVTX1_B-
009:O9
009:E7
LVTX3_D-
009:E12
009:O11
009:O5
009:E10
LVTX2_CLK-
009:E21
009:E8
009:E16
009:E10
LVTX4_D-
009:E6
009:E15
009:E16
LVTX3_E-
009:E11
009:O5
LV
009:E22
LVTX3_A-
009:E16
LVTX2_E-
009:E17
009:E8
009:E11
009:O9
009:E14
LV
009:E21
LVTX4_C-
009:E7
LV
009:E5
LVTX1_C-
009:O8
009:E11
LV
009:E20
LVTX4_E-
009:E11
LVTX3_C-
009:E8
009:E6
LVTX2_C-
009:E14
LVTX4_B-
009:E8
LVTX1_E-
009:O6
LVTX3_B-
009:E12
LVTX2_D-
009:E15
009:O8
009:E12
LVTX2_A-
009:E17
LVTX4_CLK-
009:E5
LVTX1_CLK-
009:E22
LVRX2_CLKP
008:V15
LVRX2_CLKM
008:V15
LVRX2_AP
008:V17
LVRX2_AM
008:V18
LVRX2_BP
008:V17
LVRX2_BM
008:V17
LVRX2_CP
008:V16
LVRX2_CM
008:V16
LVRX2_DP
008:V14
LVRX2_DM
008:V15
LVRX2_EP
008:V14
LVRX2_EM
008:V14
LV
009:E36
LVTX5_CLK-
009:E37
009:E35
LVTX5_A-
009:E35
009:E35
LVTX5_B-
009:E35
009:E33
LVTX5_C-
009:E34
009:E5
LVTX5_D-
009:E5
009:E33
LVTX5_E-
009:E33
LV
009:H22
LVTX6_CLK-
009:H22
009:E32
LVTX6_A-
009:E32
009:E28
LVTX6_B-
009:E29
009:E27
LVTX6_C-
009:E27
009:E31
LVTX6_D-
009:E31
009:E36
LVTX6_E-
009:E36
LV
009:H21
LVTX7_CLK-
009:H21
009:E31
LVTX7_A-
009:E32
009:E29
LVTX7_B-
009:E30
009:E29
LVTX7_C-
009:E29
009:E26
LVTX7_D-
009:E27
009:E26
LVTX7_E-
009:E26
LV
009:O24
LVTX8_CLK-
009:O23
009:E28
LVTX8_A-
009:E28
009:O34
LVTX8_B-
009:O34
009:E25
LVTX8_C-
009:E26
009:O35
LVTX8_D-
009:O35
009:O33
LVTX8_E-
009:O33
+3.3VD
SPI_DI
001:H18;001:AO37
SPI_CS
001:H19;001:AO35
SPI_SCLK
001:H19;001:AO36
SPI_DO
001:H18;001:AO36
+3.3VD
SPI_CS
001:AO35;001:AX5
R115
33
R116
33
R189
33
R192
3.3K
R190
10K
C1161
0.1uF
R191
1M
XTAL_OUT
001:H17
XTAL_IN
001:H17
XTAL_IN
001:AX10
R104
100
R108
100
R112
100
R113
100
R114
100
R120
100
R170
100
R171
100
R172
100
R174
100
R176
100
R179
100
+1.8V_DDRS
+1.0VDC
+1.0VDC
+2.5LVDS_TX
+3.3V_IO
+1.8V_DDR
C100
0.1uF
16V
C105
0.1uF
16V
C106
0.1uF
16V
C109
0.1uF
16V
C114
0.1uF
16V
C117
0.1uF
16V
C120
0.1uF
16V
C126
0.1uF
16V
C127
0.1uF
16V
C130
0.1uF
16V
C133
0.1uF
16V
C145
0.1uF
16V
C148
0.1uF
16V
C151
0.1uF
16V
C154
0.1uF
16V
C156
0.1uF
16V
C159
0.1uF
16V
C162
0.1uF
16V
C165
0.1uF
16V
C168
0.1uF
16V
C137
0.1uF
16V
C142
0.1uF
16V
C139
0.1uF
16V
C101
0.1uF
16V
C103
0.1uF
16V
C107
0.1uF
16V
C110
0.1uF
16V
C115
0.1uF
16V
C119
0.1uF
16V
C121
0.1uF
16V
C124
0.1uF
16V
C128
0.1uF
16V
C131
0.1uF
16V
C134
0.1uF
16V
C136
0.1uF
16V
C140
0.1uF
16V
C143
0.1uF
16V
C146
0.1uF
16V
C157
0.1uF
16V
C160
0.1uF
16V
C102
0.1uF
16V
C104
0.1uF
16V
C108
0.1uF
16V
C111
0.1uF
16V
C116
0.1uF
16V
C118
0.1uF
16V
C122
0.1uF
16V
C125
0.1uF
16V
C129
0.1uF
16V
C138
0.1uF
16V
C132
0.1uF
16V
C135
0.1uF
16V
C183
0.1uF
16V
C186
0.1uF
16V
C189
0.1uF
16V
C193
0.1uF
16V
C195
0.1uF
16V
C198
0.1uF
16V
C1101
0.1uF
16V
C1104
0.1uF
16V
C1107
0.1uF
16V
C1110
0.1uF
16V
C1113
0.1uF
16V
C1116
0.1uF
16V
C184
0.1uF
16V
C187
0.1uF
16V
C190
0.1uF
16V
C192
0.1uF
16V
C196
0.1uF
16V
C199
0.1uF
16V
C1102
0.1uF
16V
C1134
0.1uF
16V
C1105
0.1uF
16V
C1108
0.1uF
16V
C1111
0.1uF
16V
C1114
0.1uF
16V
C1137
0.1uF
16V
C1117
0.1uF
16V
C1119
0.1uF
16V
C1123
0.1uF
16V
C1125
0.1uF
16V
C1141
0.1uF
16V
C1130
0.1uF
16V
C1131
0.1uF
16V
C185
0.1uF
16V
C188
0.1uF
16V
C191
0.1uF
16V
C194
0.1uF
16V
C197
0.1uF
16V
C1100
0.1uF
16V
C1103
0.1uF
16V
C1106
0.1uF
16V
C1109
0.1uF
16V
C1138
0.1uF
16V
C1112
0.1uF
16V
C1115
0.1uF
16V
C1118
0.1uF
16V
C1120
0.1uF
16V
C1142
0.1uF
16V
C1124
0.1uF
16V
C1126
0.1uF
16V
C1128
0.1uF
16V
C1132
0.1uF
16V
C1135
0.1uF
16V
+0.9VREFS
+0.9VREF
DDRS_CLK
002:F12;002:AK13
DDRS_CLK
002:F12;002:AK12
DDRS_DQS0
002:F10
DDRS_DQS0
002:F9
DDRS_DQS1
002:F10
DDRS_DQS1
002:F9
DDRS_DQS2
002:AK10
DDRS_DQS2
002:AK9
DDRS_DQS3
002:AK10
DDRS_DQS3
002:AK9
DDRS_CKE
002:F12;002:U7;002:AK12;002:BB6
DDRS_CS
002:F11;002:U7;002:AK12;002:BB6
DDRS_WE
002:F11;002:U6;002:AK11;002:BB5
DDRS_RAS
002:F11;002:U6;002:AK11;002:BB5
DDRS_CAS
002:F11;002:U6;002:AK11;002:BB5
DDRS_ODT
002:F11;002:U5;002:AK12;002:BB4
DDRS_DM0
002:F9
DDRS_DM1
002:F9
DDRS_DM2
002:AK10
DDRS_DM3
002:AK10
DDRS_BA0
002:F13;002:U8;002:AK13;002:BB7
DDRS_BA1
002:F13;002:U7;002:AK13;002:BB6
DDR_CLK
002:F35;002:AI35
DDR_CLK
002:F35;002:AI35
DDR_DQS0
002:F33
DDR_DQS0
002:F32
DDR_DQS1
002:F33
DDR_DQS1
002:F32
DDR_DQS2
002:AI33
DDR_DQS2
002:AI32
DDR_DQS3
002:AI33
DDR_DQS3
002:AI32
DDR_CKE
DDR_CS
002:F34;002:U33;002:AI34;002:BB33
DDR_WE
002:F34;002:U32;002:AI34;002:BB32
DDR_RAS
002:F34;002:U31;002:AI34;002:BB32
DDR_CAS
002:F34;002:U32;002:AI34;002:BB32
DDR_ODT
DDR_DM0
002:F32
DDR_DM1
002:F32
DDR_DM2
002:AI32
DDR_DM3
002:AI32
DDR_BA0
002:F36;002:U33;002:AI36;002:BB34
DDR_BA1
002:F36;002:U33;002:AI36;002:BB33
FRC_RESET
008:W24
R177
4.7K
OPT
R178
4.7K
+3.3VD
R188
4.7K
R102
3.3K
R103
3.3K
R105
3.3K
R109
3.3K
C170
0.1uF
16V
C173
0.1uF
16V
C176
0.1uF
16V
C179
0.1uF
16V
C181
0.1uF
16V
C182
10uF
10V
C149
10uF
10V
+2.5LVDS_RX
C163
0.1uF
16V
C166
0.1uF
16V
C175
0.1uF
16V
+2.5VPLL
C172
0.1uF
16V
C177
0.1uF
16V
C144
0.1uF
16V
C164
0.1uF
16V
C155
0.1uF
16V
C150
0.1uF
16V
C141
0.1uF
16V
C158
0.1uF
16V
C153
0.1uF
16V
C167
0.1uF
16V
C147
0.1uF
16V
C161
0.1uF
16V
C169
10uF
10V
C1127
0.1uF
16V
C1143
0.1uF
16V
C1139
0.1uF
16V
C1133
0.1uF
16V
C1129
0.1uF
16V
C1151
10uF
10V
C1140
0.1uF
16V
C1148
0.1uF
16V
C1121
0.1uF
16V
C1122
0.1uF
16V
C1136
0.1uF
16V
C1146
10uF
10V
C1144
0.1uF
16V
C1149
10uF
10V
C1150
10uF
10V
C1145
0.1uF
16V
C1147
10uF
10V
C1157
0.1uF
16V
C1158
0.1uF
16V
+1.0VPLL
R121
3.3K
WP_EEPROM_TCON
004:AL21;005:AJ5
C1159
15pF
50V
C1160
15pF
50V
IC100
KIA7029AF
OPT
2
G
3
O
1
I
R106
10K
OPT
R111
33
OPT
+3.3VD
+3.3VD
R
1
2
5
2
2
R
1
2
7
2
2
R
1
2
9
2
2
R
1
3
1
2
2
R
1
3
3
2
2
R
1
3
5
2
2
R
1
3
7
2
2
R
1
3
9
2
2
R
1
4
1
2
2
R
1
4
3
2
2
R
1
4
5
2
2
R
1
4
7
2
2
R
1
4
9
2
2
R
1
5
1
2
2
R
1
5
3
2
2
R
1
5
5
2
2
R
1
5
7
2
2
R
1
5
9
2
2
R
1
6
1
2
2
R
1
6
3
2
2
R
1
6
5
2
2
R
1
6
7
2
2
R
1
6
9
2
2
R124
22
R126
22
R128
22
R130
22
R132
22
R134
22
R136
22
R138
22
R140
22
R142
22
R144
22
R146
22
R148
22
R150
22
R152
22
R154
22
R156
22
R158
22
R160
22
R162
22
R164
22
R166
22
R168
22
VSYNC
008:Y25
R117
33
R118
33
SPI_SCLK
001:AO36;001:BD4
R175
10K
PWM_SEQ
004:K10;005:I9
+3.3VD
UART_TX
001:E12
UART_RX
001:H18
R101
1K
OPT
UART_TX
001:H18
UART_RX
001:E12
C113
0.1uF
50V
R123
33
R173
33
XTAL_OUT
001:BA10
TMODE[0]
001:AO38
SPI_DI
001:AO37;001:AX5
SPI_DO
001:AO36;001:BD4
R193
22
R194
22
R195
22
R196
22
R197
22
R198
22
R199
22
R1100
22
R1101
22
R1102
22
R1103
22
R1104
22
R1105
22
R1106
22
R1107
22
R1108
22
R1109
22
R1110
22
R1111
22
R1112
22
R1113
22
R1114
22
R1115
22
R1116
22
R1117
22
R1118
22
R1119
22
R1120
22
R1121
22
R1122
22
R1123
22
R1124
22
R1125
22
R1126
22
R1127
22
R1128
22
R1129
22
R1130
22
R1131
22
R1132
22
R1133
22
R1134
22
R1135
22
R1136
22
R
1
1
3
7
2
2
R
1
1
8
0
2
2
R
1
1
7
9
2
2
R
1
1
7
8
2
2
R
1
1
7
7
2
2
R
1
1
7
6
2
2
R
1
1
7
5
2
2
R
1
1
7
4
2
2
R
1
1
7
3
2
2
R
1
1
7
2
2
2
R
1
1
7
1
2
2
R
1
1
7
0
2
2
R
1
1
6
9
2
2
R
1
1
6
8
2
2
R
1
1
6
7
2
2
R
1
1
6
6
2
2
R
1
1
6
5
2
2
R
1
1
6
4
2
2
R
1
1
6
3
2
2
R
1
1
6
2
2
2
R
1
1
6
1
2
2
R
1
1
6
0
2
2
R
1
1
5
9
2
2
R
1
1
5
8
2
2
R
1
1
5
7
2
2
R
1
1
5
6
2
2
R
1
1
5
5
2
2
R
1
1
5
4
2
2
R
1
1
5
3
2
2
R
1
1
5
2
2
2
R
1
1
5
1
2
2
R
1
1
5
0
2
2
R
1
1
4
9
2
2
R
1
1
4
8
2
2
R
1
1
4
7
2
2
R
1
1
4
6
2
2
R
1
1
4
5
2
2
R
1
1
4
4
2
2
R
1
1
4
3
2
2
R
1
1
4
2
2
2
R
1
1
4
1
2
2
R
1
1
4
0
2
2
R
1
1
3
9
2
2
R
1
1
3
8
2
2
R119 10K
R122
33
C112
0.1uF
50V
OPT
SW100
JTP-1127WEM
OPT
1
2
4
3
+1.0VDC
+3.3VD
+2.5LVDS_TX
+3.3V
L102
120-ohm
L104
120-ohm
+3.3V_IO
+2.5VQ
L100
120-ohm
L101
120-ohm
+2.5LVDS_RX
C1167
0.1uF
16V
L105
120-ohm
L103
120-ohm
+1.0VPLL
+2.5VPLL
FPGA_SCL
FPGA_SDA
R1183
0 OPT
R1184
0 OPT
R1181
3.3K
OPT
R1182
3.3K
OPT
/FPGA_RESET
009:AN29
R1185
10K
OPT
R1186
33
TMODE[0] 001:H22
SPI_DI 001:H18;001:AX5
TCON_SDA
004:AE9
SPI_SCLK
001:H19;001:BD4
SPI_CS 001:H19;001:AX5
SPI_DO 001:H18;001:BD4
TCON_SCL
004:AA9
3D_FRAME_INFO
010:AN12
I2C_SCL
005:AA16;008:F18;008:V24;008:AL4;009:AP8
I2C_SDA
005:AA15;008:N18;008:V25;008:AL4;009:AP11
R1190
33
TCON_POWER_EN
007:Q15;006:P14
R1191
33
R1197
10K
OPT
R1193
33
R1192
33
R1194
33
R1195
33
R1196
33
+3.3VD
IC101
W25X20AVSNIG
3
WP
2
DO
4
GND
1
CS
5
DIO
6
CLK
7
HOLD
8
VCC
R180
33
LVDS_OUT
LVDS_IN
VIDEO_OUT
R1187
4.7K
OPT
R1199
4.7K
+3.3VD
VIDEO_OUT
R1198
4.7K
+3.3VD
R1189
4.7K
OPT
R1188
4.7K
LVDS_IN
LVDS_OUT
R1200
4.7K
OPT
+3.3VD
X100
25MHz
IC102
LG1120
RCLK1P
AN18
RCLK1M
AP18
RA1P
AP15
RA1M
AN15
RB1P
AP16
RB1M
AN16
RC1P
AP17
RC1M
AN17
RD1P
AN19
RD1M
AP19
RE1P
AN20
RE1M
AP20
TCLK1P
A4
TCLK1N
B4
TA1P
A2
TA1N
B2
TB1P
C3
TB1N
C2
TC1P
B3
TC1N
A3
TD1P
C5
TD1N
C4
TE1P
B5
TE1N
A5
TCLK2P
A8
TCLK2N
B8
TA2P
A6
TA2N
B6
TB2P
C7
TB2N
C6
TC2P
B7
TC2N
A7
TD2P
C9
TD2N
C8
TE2P
B9
TE2N
A9
TCLK3P
A12
TCLK3N
B12
TA3P
A10
TA3N
B10
TB3P
C11
TB3N
C10
TC3P
B11
TC3N
A11
TD3P
C13
TD3N
C12
TE3P
B13
TE3N
A13
TCLK4P
A16
TCLK4N
B16
TA4P
A14
TA4N
B14
TB4P
C15
TB4N
C14
TC4P
B15
TC4N
A15
TD4P
C17
TD4N
C16
TE4P
B17
TE4N
A17
SMODE
AL12
TMODE[0]
AN10
TMODE[1]
AP10
TMODE[2]
AL11
TMODE[3]
AM11
TRST_N
AP31
TCK
AN31
TMS
AM31
TDI
AK31
TDO
AL31
M_SCL
AN8
M_SDA
AM8
SCL
AL9
SDA
AP8
SPI_CS
AL10
SPI_SCLK
AP9
SPI_DI
AN9
SPI_DO
AM9
UART_RXD
AL8
UART_TXD
AP7
PORES_N
AM10
XTALI
AP11
XTALO
AN11
DDRS_VREF0
L4
DDRS_VREF1
V4
DDRS_VREF2
AE4
DDRS_A[0]
W1
DDRS_A[1]
T1
DDRS_A[2]
W2
DDRS_A[3]
T2
DDRS_A[4]
R1
DDRS_A[5]
T3
DDRS_A[6]
R2
DDRS_A[7]
Y2
DDRS_A[8]
U1
DDRS_A[9]
Y3
DDRS_A[10]
R3
DDRS_A[11]
U2
DDRS_A[12]
AC1
DDRS_DQ[0]
F3
DDRS_DQ[1]
H4
DDRS_DQ[2]
E1
DDRS_DQ[3]
J4
DDRS_DQ[4]
H3
DDRS_DQ[5]
E2
DDRS_DQ[6]
G4
DDRS_DQ[7]
F2
DDRS_DQ[8]
K3
DDRS_DQ[9]
N2
DDRS_DQ[10]
J1
DDRS_DQ[11]
M1
DDRS_DQ[12]
N1
DDRS_DQ[13]
J2
DDRS_DQ[14]
M2
DDRS_DQ[15]
K2
DDRS_DQ[16]
AJ2
DDRS_DQ[17]
AM1
DDRS_DQ[18]
AH4
DDRS_DQ[19]
AN1
DDRS_DQ[20]
AM2
DDRS_DQ[21]
AH3
DDRS_DQ[22]
AL2
DDRS_DQ[23]
AJ1
DDRS_DQ[24]
AE2
DDRS_DQ[25]
AH1
DDRS_DQ[26]
AD1
DDRS_DQ[27]
AG2
DDRS_DQ[28]
AG1
DDRS_DQ[29]
AD2
DDRS_DQ[30]
AH2
DDRS_DQ[31]
AE1
DDRS_CK
V1
DDRS_CK_N
V2
DDRS_DQS[0]
G2
DDRS_DQS_N[0]
G1
DDRS_DQS[1]
L1
DDRS_DQS_N[1]
L2
DDRS_DQS[2]
AK3
DDRS_DQS_N[2]
AK4
DDRS_DQS[3]
AF4
DDRS_DQS_N[3]
AF3
DDRS_CKE
Y1
DDRS_CS_N
AA1
DDRS_WE_N
AC2
DDRS_RAS_N
AB2
DDRS_CAS_N
AA2
DDRS_ODT
AB1
DDRS_DM[1]
M3
DDRS_DM[0]
F4
DDRS_DM[2]
AJ3
DDRS_DM[3]
AE3
DDRS_BA[0]
V3
DDRS_BA[1]
W3
DDRS_TAOUT
N3
DDRS_TDOUT[0]
AB3
DDRS_TDOUT[1]
AC3
RCLK2P
AN24
RCLK2M
AP24
RA2P
AN21
RA2M
AP21
RB2P
AN22
RB2M
AP22
RC2P
AN23
RC2M
AP23
RD2P
AN25
RD2M
AP25
RE2P
AN26
RE2M
AP26
TCLK5P
A20
TCLK5N
B20
TA5P
A18
TA5N
B18
TB5P
C19
TB5N
C18
TC5P
B19
TC5N
A19
TD5P
C21
TD5N
C20
TE5P
B21
TE5N
A21
TCLK6P
A24
TCLK6N
B24
TA6P
A22
TA6N
B22
TB6P
C23
TB6N
C22
TC6P
B23
TC6N
A23
TD6P
C25
TD6N
C24
TE6P
B25
TE6N
A25
TCLK7P
A28
TCLK7N
B28
TA7P
A26
TA7N
B26
TB7P
C27
TB7N
C26
TC7P
B27
TC7N
A27
TD7P
C29
TD7N
C28
TE7P
B29
TE7N
A29
TCLK8P
A32
TCLK8N
B32
TA8P
A30
TA8N
B30
TB8P
C31
TB8N
C30
TC8P
B31
TC8N
A31
TD8P
C33
TD8N
C32
TE8P
B33
TE8N
A33
M_VS
AL30
M_SCLK
AM30
M_MOSI
AN30
S_VS
AP5
S_SCLK
AN5
S_MOSI
AM5
GPIO[0]
AL4
GPIO[1]
AM4
GPIO[2]
AN4
GPIO[3]
AP4
GPIO[4]
AL5
GPIO[5]
AL6
GPIO[6]
AM6
GPIO[7]
AN6
GPIO[8]
AP6
GPIO[9]
AL7
GPIO[10]
AM7
GPIO[11]
AN7
GPIO[12]
AL27
GPIO[13]
AN28
GPIO[14]
AP29
GPIO[15]
AN29
GPIO[16]
AN27
GPIO[17]
AP27
GPIO[18]
AP30
GPIO[19]
AM27
GPIO[20]
AP28
GPIO[21]
AM28
GPIO[22]
AL28
GPIO[23]
AM29
GPIO[24]
AL29
DDR_VREF0
AF31
DDR_VREF1
W31
DDR_VREF2
K31
DDR_A[0]
U34
DDR_A[1]
Y34
DDR_A[2]
U33
DDR_A[3]
Y33
DDR_A[4]
AA34
DDR_A[5]
Y32
DDR_A[6]
AA33
DDR_A[7]
T33
DDR_A[8]
W34
DDR_A[9]
T32
DDR_A[10]
AA32
DDR_A[11]
W33
DDR_A[12]
N34
DDR_DQ[0]
AM33
DDR_DQ[1]
AH32
DDR_DQ[2]
AN34
DDR_DQ[3]
AG32
DDR_DQ[4]
AJ32
DDR_DQ[5]
AN33
DDR_DQ[6]
AK32
DDR_DQ[7]
AM34
DDR_DQ[8]
AG33
DDR_DQ[9]
AC33
DDR_DQ[10]
AH34
DDR_DQ[11]
AD34
DDR_DQ[12]
AC34
DDR_DQ[13]
AJ33
DDR_DQ[14]
AD33
DDR_DQ[15]
AG34
DDR_DQ[16]
G33
DDR_DQ[17]
F34
DDR_DQ[18]
H31
DDR_DQ[19]
E34
DDR_DQ[20]
E33
DDR_DQ[21]
H32
DDR_DQ[22]
F33
DDR_DQ[23]
G34
DDR_DQ[24]
K33
DDR_DQ[25]
H34
DDR_DQ[26]
L34
DDR_DQ[27]
J33
DDR_DQ[28]
J34
DDR_DQ[29]
L33
DDR_DQ[30]
H33
DDR_DQ[31]
K34
DDR_CK
V34
DDR_CK_N
V33
DDR_DQS[0]
AL33
DDR_DQS_N[0]
AL34
DDR_DQS[1]
AF34
DDR_DQS_N[1]
AF33
DDR_DQS[2]
F32
DDR_DQS_N[2]
F31
DDR_DQS[3]
J31
DDR_DQS_N[3]
J32
DDR_CKE
T34
DDR_CS_N
R34
DDR_WE_N
N33
DDR_RAS_N
P33
DDR_CAS_N
R33
DDR_ODT
P34
DDR_DM[0]
AM32
DDR_DM[1]
AD32
DDR_DM[2]
G32
DDR_DM[3]
K32
DDR_BA[0]
V32
DDR_BA[1]
U32
DDR_TAOUT
AC32
DDR_TDOUT[0]
N32
DDR_TDOUT[1]
P32
IC102
LG1120
VDD33_1
D3
VDD33_2
D4
VDD33_3
D5
VDD33_4
D6
VDD33_5
D7
VDD33_6
D28
VDD33_7
D29
VDD33_8
D30
VDD33_9
D31
VDD33_10
D32
VDD33_11
AJ5
VDD33_12
AK5
VDD33_13
AK6
VDD33_14
AK7
VDD33_15
AK8
VDD33_16
AK9
VDD33_17
AK10
VDD33_18
AJ30
VDD33_19
AK27
VDD33_20
AK28
VDD33_21
AK29
VDD33_22
AK30
LVTX_VDD_1
D8
LVTX_VDD_2
D10
LVTX_VDD_3
D12
LVTX_VDD_4
D14
LVTX_VDD_5
D20
LVTX_VDD_6
D22
LVTX_VDD_7
D24
LVTX_VDD_8
D26
PVCC1
D16
PVCC2
D18
VDD_1
E9
VDD_2
E11
VDD_3
E13
VDD_4
E15
VDD_5
E17
VDD_6
E19
VDD_7
E21
VDD_8
E23
VDD_9
E25
VDD_10
E27
VDD_11
G5
VDD_12
H5
VDD_13
J5
VDD_14
K5
VDD_15
L5
VDD_16
M5
VDD_17
N5
VDD_18
P5
VDD_19
R5
VDD_20
T5
VDD_21
U5
VDD_22
V5
VDD_23
W5
VDD_24
Y5
VDD_25
AA5
VDD_26
AB5
VDD_27
AC5
VDD_28
AD5
VDD_29
AE5
VDD_30
AG5
VDD_31
AF5
VDD_32
G30
VDD_33
H30
VDD_34
J30
VDD_35
K30
VDD_36
L30
VDD_37
M30
VDD_38
N30
VDD_39
P30
VDD_40
R30
VDD_41
T30
VDD_42
U30
VDD_43
V30
VDD_44
W30
VDD_45
Y30
VDD_46
AA30
VDD_47
AB30
VDD_48
AC30
VDD_49
AD30
VDD_50
AE30
VDD_51
AF30
VDD_52
AG30
VDD_53
AL14
VDD_54
AL15
VDD_55
AL16
VDD_56
AL17
VDD_57
AL18
VDD_58
AL19
VDD_59
AL20
VDD_60
AL21
VDD_61
AL22
VDD_62
AL23
VDD_63
AL24
VDD_64
AM15
VDD_65
AM16
VDD_66
AM25
VDD_67
AM26
LVRX_VDD1
AM18
LVRX_VDD2
AM20
LVRX_VDD3
AM22
LVRX_VDD4
AM24
DDRS_VDDQ_1
H1
DDRS_VDDQ_2
K4
DDRS_VDDQ_3
L3
DDRS_VDDQ_4
M4
DDRS_VDDQ_5
N4
DDRS_VDDQ_6
P4
DDRS_VDDQ_7
R4
DDRS_VDDQ_8
T4
DDRS_VDDQ_9
U3
DDRS_VDDQ_10
U4
DDRS_VDDQ_11
Y4
DDRS_VDDQ_12
AA3
DDRS_VDDQ_13
AA4
DDRS_VDDQ_14
AB4
DDRS_VDDQ_15
AC4
DDRS_VDDQ_16
AD4
DDRS_VDDQ_17
AF1
DDRS_VDDQ_18
AG4
DDRS_VDDQ_19
AJ4
DDRS_VDDQ_20
AK1
DDRS_VDDQ_21
P1
DDRS_VDDQ_22
P3
DDR_VDDQ_1
L31
DDR_VDDQ_2
M31
DDR_VDDQ_3
M34
DDR_VDDQ_4
N31
DDR_VDDQ_5
P31
DDR_VDDQ_6
R31
DDR_VDDQ_7
R32
DDR_VDDQ_8
T31
DDR_VDDQ_9
U31
DDR_VDDQ_10
V31
DDR_VDDQ_11
Y31
DDR_VDDQ_12
AA31
DDR_VDDQ_13
AB31
DDR_VDDQ_14
AB34
DDR_VDDQ_15
AC31
DDR_VDDQ_16
AD31
DDR_VDDQ_17
AE31
DDR_VDDQ_18
AE32
DDR_VDDQ_19
AE34
DDR_VDDQ_20
AG31
DDR_VDDQ_21
AH31
DDR_VDDQ_22
AK34
SS_DISP_DVDD
AM14
DDRPLL_DVDD
AN12
DDRPLL_AVDD
AL13
SS_AVDD
AN13
DISP_AVDD
AP14
IC102
LG1120
VSS_1
B1
VSS_2
B34
VSS_3
C1
VSS_4
C34
VSS_5
D1
VSS_6
D2
VSS_7
D33
VSS_8
D34
VSS_9
E3
VSS_10
E4
VSS_11
E5
VSS_12
E6
VSS_13
E7
VSS_14
E8
VSS_15
E10
VSS_16
E12
VSS_17
E14
VSS_18
E16
VSS_19
E18
VSS_20
E20
VSS_21
E22
VSS_22
E24
VSS_23
E26
VSS_24
E28
VSS_25
E29
VSS_26
E30
VSS_27
E31
VSS_28
E32
VSS_29
F1
VSS_30
F5
VSS_31
F30
VSS_32
G3
VSS_33
G31
VSS_34
H2
VSS_35
J3
VSS_36
K1
VSS_37
L32
VSS_38
M12
VSS_39
M13
VSS_40
M14
VSS_41
M15
VSS_42
M16
VSS_43
M17
VSS_44
M18
VSS_45
M19
VSS_46
M20
VSS_47
M21
VSS_48
M22
VSS_49
M23
VSS_50
M32
VSS_51
M33
VSS_52
N12
VSS_53
N13
VSS_54
N14
VSS_55
N15
VSS_56
N16
VSS_57
N17
VSS_58
N18
VSS_59
N19
VSS_60
N20
VSS_61
N21
VSS_62
N22
VSS_63
N23
VSS_64
P2
VSS_65
P12
VSS_66
P13
VSS_67
P14
VSS_68
P15
VSS_69
P16
VSS_70
P17
VSS_71
P18
VSS_72
P19
VSS_73
P20
VSS_74
P21
VSS_75
P22
VSS_76
P23
VSS_77
R12
VSS_78
R13
VSS_79
R14
VSS_80
R15
VSS_81
R16
VSS_82
R17
VSS_83
R18
VSS_84
R19
VSS_85
R20
VSS_86
R21
VSS_87
R22
VSS_88
R23
VSS_89
T12
VSS_90
T13
VSS_91
T14
VSS_92
T15
VSS_93
T16
VSS_94
T17
VSS_95
T18
VSS_96
T19
VSS_97
T20
VSS_98
T21
VSS_99
T22
VSS_100
T23
VSS_101
U12
VSS_102
U13
VSS_103
U14
VSS_104
U15
VSS_105
U16
VSS_106
U17
VSS_107
U18
VSS_108
U19
VSS_109
U20
VSS_110
U21
VSS_111
U22
VSS_112
U23
VSS_113
V12
VSS_114
V13
VSS_115
V14
VSS_116
V15
VSS_117
V16
VSS_118
V17
VSS_119
V18
VSS_120
V19
VSS_121
V20
VSS_122
V21
VSS_123
V22
VSS_124
V23
VSS_125
W4
VSS_126
W12
VSS_127
W13
VSS_128
W14
VSS_129
W15
VSS_130
W16
VSS_131
W17
VSS_132
W18
VSS_133
W19
VSS_134
W20
VSS_135
W21
VSS_136
W22
VSS_137
W23
VSS_138
W32
VSS_139
Y12
VSS_140
Y13
VSS_141
Y14
VSS_142
Y15
VSS_143
Y16
VSS_144
Y17
VSS_145
Y18
VSS_146
Y19
VSS_147
Y20
VSS_148
Y21
VSS_149
Y22
VSS_150
Y23
VSS_151
AA12
VSS_152
AA13
VSS_153
AA14
VSS_154
AA15
VSS_155
AA16
VSS_156
AA17
VSS_157
AA18
VSS_158
AA19
VSS_159
AA20
VSS_160
AA21
VSS_161
AA22
VSS_162
AA23
VSS_163
AB12
VSS_164
AB13
VSS_165
AB14
VSS_166
AB15
VSS_167
AB16
VSS_168
AB17
VSS_169
AB18
VSS_170
AB19
VSS_171
AB20
VSS_172
AB21
VSS_173
AB22
VSS_174
AB23
VSS_175
AB32
VSS_176
AB33
VSS_177
AC12
VSS_178
AC13
VSS_179
AC14
VSS_180
AC15
VSS_181
AC16
VSS_182
AC17
VSS_183
AC18
VSS_184
AC19
VSS_185
AC20
VSS_186
AC21
VSS_187
AC22
VSS_188
AC23
VSS_189
AD3
VSS_190
AE33
VSS_191
AF2
VSS_192
AF32
VSS_193
AG3
VSS_194
AH5
VSS_195
AH30
VSS_196
AH33
VSS_197
AJ31
VSS_198
AJ34
VSS_199
AK2
VSS_200
AK11
VSS_201
AK12
VSS_202
AK13
VSS_203
AK14
VSS_204
AK15
VSS_205
AK16
VSS_206
AK17
VSS_207
AK18
VSS_208
AK19
VSS_209
AK20
VSS_210
AK21
VSS_211
AK22
VSS_212
AK23
VSS_213
AK24
VSS_214
AK25
VSS_215
AK26
VSS_216
AK33
VSS_217
AL1
VSS_218
AL3
VSS_219
AL25
VSS_220
AL26
VSS_221
AL32
VSS_222
AM3
VSS_223
AN2
VSS_224
AN3
VSS_225
AN32
VSS_226
AP2
VSS_227
AP3
VSS_228
AP32
VSS_229
AP33
LVTX_VSS_1
D9
LVTX_VSS_2
D11
LVTX_VSS_3
D13
LVTX_VSS_4
D15
LVTX_VSS_5
D21
LVTX_VSS_6
D23
LVTX_VSS_7
D25
LVTX_VSS_8
D27
PGND1
D17
PGND2
D19
LVRX_VSS1
AM17
LVRX_VSS2
AM19
LVRX_VSS3
AM21
LVRX_VSS4
AM23
DDRPLL_DVSS
AM12
SS_AVSS
AM13
DISP_AVSS
AN14
DDRPLL_AVSS
AP12
SS_DISP_DVSS
AP13
C123
0.1uF
50V
OPT
FRC_TCK
R1212
22
R1213
22
FRC_TDI
FRC_TDO
P102
YFW254-06
OPT
1
2
3
4
5
6
FRC_TMS
R1210
22
R1211
22
+3.3VD
FPGA_D/L_CTRL
R1214
0
INCH_OPT_2
TCON_SCL_S
TCON_SDA_S
R1218
33
TCON_SDA_M
R1216
33
R1217
33
INCH_OPT_1
TCON_SCL_M
R1215
33
INCH_OPT_1
+3.3VD
+3.3VD
R1205
4.7K
INCH_1_LOW
R1206
4.7K
INCH_2_HIGH
R1207
4.7K
INCH_2_LOW
R1204
4.7K
INCH_1_HIGH
INCH_OPT_2
FRC_TDI
FRC_TCK
FRC_TDO
FRC_TMS
I2CEN
R1201
33
R1219
33
L/R_SYNC
R1220
33
P100
12505WR-04A00
OPT
1
+3.3V
2
GND
3
RX
4
TX
5
.
P101
12505WR-10
1
2
3
4
5
6
7
8
9
10
11
M_TCON_EN
005:AA14
S_TCON_EN
005:AG12
R1221
33
L/R_SYNC_FRC_OUT
C1162
22uF
16V
C1164
22uF
16V
C1154
22uF
16V
C1163
22uF
16V
C1165
22uF
16V
C180
22uF
16V
C178
22uF
16V
C1153
22uF
16V
C1166
22uF
16V
C152
22uF
16V
C1155
22uF
16V
C1152
22uF
16V
C171
22uF
16V
C174
22uF
16V
R1222
10K
+3.3VD
R1224
0
OPT
R1223
0
DPM_CTRL
004:AM14
R107
1K
R110
1K
R1225
10K
+3.3VD
R1226 0
OPT
R1227 0
OPT
DPM_CTRL1
008:M17
GAMMA_BKSEL
008:M17
3D + 240 FRC + TCON BOARD
2009. 11. 13
LG1120(FRC 240Hz Chip)
1
SPI FLASH(2Mbit)
XTAL
Serial Flash Boot Mode
- GPIO[0]=1 : 50MHz Booting
- GPIO[0]=0 : 25MHz Booting
[TEST MODE SETTING]
- SMODE = 0 : Serial Flash Setting
- TMODE(All) = 1 : Normal Mode
10
For 3D Formatter
For 3D Formatter I2C (Ready)
Output LVDS Data Mapping Selection
- GPIO[6] = 1 : JEIDA
- GPIO[6] = 0 : VESA
Video Output Selection
- GPIO[7] = 1 : Reverse(LED Model)
- GPIO[7] = 0 : Normal(LAMP Model)
Input LVDS Data Mapping Selection
- GPIO[5] = 1 : JEIDA
- GPIO[5] = 0 : VESA
LOW
42
HIGH
LOW
INCH_2
47
INCH_1
HIGH
55
LOW
LOW
OD data D/L,
during 2D/3D mode switching
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Содержание 42LX6500
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