THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2009.09.11
URSA3 DDR & Power
COMMON
89
DDR3_A[9]
DDR3_DQU[4]
DDR3_DQL[4]
DDR3_DQU[6]
DDR3_A[0]
DDR3_DQL[2]
DDR3_A[8]
DDR3_DQU[1]
DDR3_A[2]
DDR3_DQL[6]
DDR3_A[1]
DDR3_DQU[2]
DDR3_A[6]
DDR3_DQL[0]
DDR3_A[10]
DDR3_A[11]
DDR3_DQU[5]
DDR3_A[5]
DDR3_DQL[3]
DDR3_DQL[1]
DDR3_DQL[5]
DDR3_A[7]
DDR3_DQU[7]
DDR3_DQL[7]
DDR3_A[3]
DDR3_DQU[3]
DDR3_DQU[0]
DDR3_A[4]
DDR3_A[12]
DDR3_DQSUB
D1.5V_DDR3
FRC_A[12]
DDR3_DQU[0]
DDR3_DML
D1.5V_DDR3
DDR3_WEB
DDR3_DQU[1]
DDR3_A[3]
DDR3_DQL[4]
DDR3_A[1]
DDR3_A[0]
R8922
150
OPT
DDR3_A[2]
DDR3_CASB
DDR3_A[9]
DDR3_A[10]
DDR3_RASB
DDR3_A[4]
DDR3_DQU[6]
DDR3_DMU
DDR3_RESETB
FRC_A[0]
C8924
0.1uF
DDR3_ODT
DDR3_A[12]
MVREFCA
DDR3_DQU[5]
FRC_BA2
DDR3_DQL[3]
FRC_DQU[3]
DDR3_DQU[4]
DDR3_DQSL
C8913
0.1uF
C8929
0.1uF
DDR3_A[7]
FRC_DQSLB
D1.5V_DDR3
C8910
1000pF
OPT
FRC_DQU[1]
DDR3_MCLK
DDR3_A[11]
DDR3_DQU[3]
FRC_DQU[5]
DDR3_DMU
FRC_DQSL
MVREFDQ
FRC_RASB
C8922
0.1uF
MVREFCA
DDR3_DQL[6]
FRC_DQL[2]
DDR3_WEB
FRC_WEB
FRC_DQU[7]
R8904
1K
1%
R8920
1K
1%
FRC_A[6]
DDR3_DQL[7]
FRC_DQSU
FRC_DML
C8930
0.1uF
DDR3_DQSU
DDR3_BA1
DDR3_DML
C8902
10uF
10V
FRC_DQL[7]
DDR3_BA0
DDR3_DQL[0]
DDR3_DQU[7]
DDR3_A[8]
C8915
0.1uF
DDR3_A[0-12]
DDR3_DQSLB
FRC_DQL[1]
FRC_DQL[3]
D1.5V_DDR3
DDR3_BA0
FRC_DQU[6]
C8928
0.1uF
FRC_ODT
DDR3_ODT
C8917
0.1uF
DDR3_DQU[0-7]
R8921
240
1%
DDR3_DQL[2]
DDR3_MCLKB
FRC_DQU[2]
FRC_CASB
FRC_CKE
FRC_MCLKB
FRC_DQU[4]
FRC_DQL[4]
C8909
0.1uF
MVREFDQ
FRC_DDR3_RESETB
FRC_DQSUB
C8921
0.1uF
DDR3_DQL[5]
FRC_A[4]
DDR3_MCLK
DDR3_DQL[1]
FRC_DQL[5]
FRC_DQL[6]
FRC_A[2]
FRC_BA1
C8919
0.1uF
FRC_BA0
C8927
0.1uF
DDR3_MCLKB
DDR3_BA2
C8925
0.1uF
R8919
1K
1%
C8918
0.1uF
DDR3_A[6]
L8900
C8908
10uF
DDR3_DQSL
DDR3_DQSU
FRC_A[11]
C8901
0.1uF
FRC_A[5]
FRC_A[10]
C8916
0.1uF
FRC_DQU[0]
D1.5V_DDR3
DDR3_DQL[0-7]
DDR3_DQU[2]
DDR3_A[5]
DDR3_DQSLB
FRC_A[8]
C8903
1000pF
OPT
FRC_MCLK
DDR3_CKE
DDR3_RESETB
FRC_A[9]
DDR3_CASB
R8900
1K
1%
C8914
0.1uF
D1.5V_DDR3
FRC_DMU
DDR3_BA2
FRC_A[3]
C8904
0.1uF
16V
+1.5V_MEMC
R8923
10K
FRC_A[1]
DDR3_DQSUB
FRC_A[7]
C8920
0.1uF
C8926
0.1uF
DDR3_CKE
DDR3_BA1
C8923
0.1uF
FRC_DQL[0]
DDR3_RASB
+1.5V_MEMC
+3.3V_MEMC
C8934
10uF
25V
C8937
2200pF
+3.3V_MEMC
+12V
R8928
10K
C8944
0.1uF
16V
R8935
10K
1%
C8942
22uF
10V
C8940
100pF
50V
OPT
L8905
3.6uH
NR8040T3R6N
C8932
10uF
25V
POWER_ON/OFF2_2
POWER_ON/OFF2_1
+1.26V_MEMC
AR8903
10
AR8900
10
AR8902
10
AR8901
10
AR8904
10
AR8905
10
AR8908
10
AR8907
10
AR8906
10
R8912
10
R8910
10
R8909
10
R8913
10
R8911
10
R8914
10
R8918
10
R8916
10
R8917
10
R8915
10
R8933
27K
1%
R8934
4.7K
1%
L8902
CIC21J501NE
R8925
9.1K
22uF
C8938
R8929
56
1%
L8903
CIC21J501NE
IC8901
AP1117EG-13
ADJ/GND
OUT
IN
R8926
10K
L8904
3.6uH
NR8040T3R6N
C8933
10uF
25V
C8939
100pF
50V
OPT
C8943
0.1uF
16V
C8931
10uF
25V
C8941
22uF
10V
+12V
R8932
12K
1%
L8901
R8931
3.9K
1%
R8924
6.2K
C8936
3300pF
H5TQ1G63BFR-12C
IC8900
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
IC8903
AOZ1072AI
3
AGND
2
VIN
4
FB
1
PGND
5
COMP
6
EN
7
LX_1
8
LX_2
IC8902
AOZ1072AI
3
AGND
2
VIN
4
FB
1
PGND
5
COMP
6
EN
7
LX_1
8
LX_2
C8935
10uF
16V
R8927
270
1%
R8930
3.3K
1%
C8946
0.1uF
16V
R8936
1
DDR3 1.5V By CAP - Place these Caps near Memory
Close to DDR Power Pin
2A
R1
R2
+3.3V_MEMC
Vout=0.8*(1+R1/R2)
URSA3 CORE 1.26V
1074 mA
URSA3 DDR3 1.5V
R2
R1
2A
Vout=0.8*(1+R1/R2)
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Содержание 42LD650
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