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Only for training and service purposes
C
LGE Internal Use Only
- 26 -
H
ig
h
C
ha
ss
is
B
C
M3
52
30
(IC1
01
)
H
ig
h
C
ha
ss
is
H
ig
h
C
ha
ss
is
B
C
M3
52
30
B
C
M3
52
30
(IC1
0
(IC1
0
1
1
)
)
N
VR
A
M
(1
M
, I
C1
03
)
N
VR
A
M
N
VR
A
M
(
(
1M
1M
, I
C1
0
, I
C1
0
3
3
)
)
NAND
FLA
SH
(8
G
bi
t, I
C
10
2)
NAND
FLA
SH
NAND
FLA
SH
(
(
8
8
G
G
bi
t
bi
t
, I
C
10
, I
C
10
2
2
)
)
NAND_
DA
TA
[0
-7
]
EE
PR
O
M
_SCL
/S
DA
LE
D
_R
/B
uz
z
KEY
1/
2
,IR
EE
PR
O
M
(IC6
01
)
EE
PR
O
M
(IC6
01
)
N
EC
_M
ic
om
IC6
02
N
EC
_M
ic
om
N
EC
_M
ic
om
IC6
02
IC6
02
IR
& KEY
P9
01
IR
& KEY
IR
& KEY
P9
01
P9
01
SCL2
/S
DA2
_3
.3
V
Po
w
er
B
/D
P5
02
Po
w
er
B
/D
Po
w
er
B
/D
P5
02
P5
02
INV_
CT
L,
R
L_
O
N
De
bu
gg
er
P6
01
De
bu
gg
er
De
bu
gg
er
P6
01
P6
01
N
EC
_I
S
P_
TX/
R
X
,O
C
D1
A/
B
,F
LM
D
0,
M
IN
C
O
M
_R
E
SET
SO
C
_
R
es
et
NAND
_
WEb
/A
LE
/CLE
…
LPF
SCL1
/S
DA1
_3
.3
V
Sp
e
a
ke
r
P1
80
1
A
udi
o
A
M
P
N
TP
-740
0L
IC1
80
2
A
udi
o
A
M
P
A
udi
o
A
M
P
N
TP
N
TP
-
-
740
0L
740
0L
IC1
80
2
IC1
80
2
AUD_
LR
C
H
/LR
CK/
SCK,
A
M
P_
M
ut
e
S
PK
_L
+
/-
S
PK
_R
+
/-
PW
M
S
DA
/SC
L1
_3
.3
V
TXA
/B
/C
/D
[0
-4
] N
/P,
TXA
/B
/C
/D
CLK
N/CLK
P
LV
D
S
_T
XA/
B
[0
-4
] N
/P,
LV
D
S
_T
XA/
B
CLK
N/CLK
P
LV
D
S
_T
XC/
D
[0
-4
] N
/P,
LV
D
S
_T
XC/
D
CLK
N/CLK
P
LG
E7
303
C
IC5
20
1
LG
E7
303
C
LG
E7
303
C
IC5
20
1
IC5
20
1
FR
C_
R
E
SET
LE
D
_B
/LG
L
O
G
O
LE
D
D
riv
ing
B
/D
P3
501
(51
PI
N
)
LE
D
D
riv
ing
B
/D
LE
D
D
riv
ing
B
/D
P3
501
(51
PI
N
)
P3
501
(51
PI
N
)
LE
D
D
riv
ing
B
/D
P3
502
(41
PI
N
)
LE
D
D
riv
ing
B
/D
LE
D
D
riv
ing
B
/D
P3
502
(41
PI
N
)
P3
502
(41
PI
N
)
Woof
er
N
TP
-740
0L
IC1
80
1
Woof
er
Woof
er
N
TP
N
TP
-
-
740
0L
740
0L
IC1
80
1
IC1
80
1
SCL1
/S
DA1
_3
.3
V
AUD_
LR
C
H
/LR
CK/
SCK,
A
M
P_
M
ut
e
SPK_
W
o
o
fe
r
+
/-
Woof
er
P1
80
2
Woof
er
Woof
er
P1
80
2
P1
80
2
AUD_
M
A
ST
ER
_CLK
AUD_
M
A
ST
ER
_CLK
SPI
F
LASH
( I
C
520
2,
2M
)
SPI
F
LASH
( I
C
520
2,
2M
)
S
PI
_DO
/C
S/
SC
LK/
D
I
S/
T_
SC
L/
S
DA
Ea
rp
hon
e
A
M
P
IC8
04
Ea
rp
hon
e
A
M
P
Ea
rp
hon
e
A
M
P
IC8
04
IC8
04
HP_
L/
R
_O
U
T_
N
/P
HP_
L/
R
O
U
T
HP
DDR3
( I
C
530
1)
DDR3
( I
C
530
1)
FR
C_
A
[0
-1
3],
FR
C_
B
A0/
1/
2,
FR
C
_M
CLK/CLE/
M
CLKB
…
(
DD
R3
_A
[0
-13
],DD
R
3_
B
A0/
1/
2,
DD
R
3_
M
CLK
…
)
FR
C_
DQ
U
/DQ
L[0
-7
]
(DD
R
3_
DQ
U/
DQ
L[
0-7
])
DD
R
( I
C4
01
,IC4
02
)
DD
R
( I
C4
01
,IC4
02
)
DD
R
_AA
…
,
DD
R
01
/23
_CLK/C
LKb,
……
DD
R
_DQ
[0
-7
]/[
8-
15
]/[1
6-
23
]/[
24
-3
1]
JK
8
03
Block diagram for LW5500 M/B_Output
Содержание 32LW5500
Страница 56: ......