LG 32LP1DC-UA, Руководство по обслуживанию

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BLOCK DIAGRAM(MAIN)
- 18 -
10
LG
HD-ll
LGDT1102
EPLD1
(XC95
1
4
4
XL)
VCXO
2
7
Mhz
CLK S
y
n
.
(LGDPLL )
2
V/Y
,
C
2
RGB-PC
5
RGBHV
2
YC
1.8
V
Reg.
Vide
o
Dec
oder
(VPX3
2
2
6
E)
X-tal
(20.
2
5
M
)
MUX
(MC14
0
5
3)
HV
H,V
,CL
P
HV
LPF
(8M)
LPF
(8M)
Activ
e
LPF
(AF93
97)
HV
ADC
(AD988
3A)
n4
80i
PC_IN
FID
CPU
TP[0
:7],
TP_CL
K,
TP_v
a
lid
Data
[0:7
],
CLK
SEL
_VSB/
1
3
9
4
,
SEL
_TP
CPU
EPLD1
[MUX,
3-sta
te]
9
3
LPF LPF
HV_P
C
HV_
p
o
l
OR1
YCbCr
24
OR2
H,V
,
CLK
3
YCbCr
16
H,V
,CL
K
3
FID
OR1 OR2 OR3
TP/D1
9
YCbCr
24
H,V
,CL
K
3
FID
RC
Filte
r
VDPClk
(74.
2
5
M
)
SysClk
FR_6
0
NT2Clk
(27M
)
EPLD
CPU
(S3C4
4B0X
)
2
CPU
X-tal (10M
)
I2C c
tr
l
(PCF85
8
4
)
RS-23
2C
(ST32
3
2
)
I2C Hu
b
(PCA95
1
6
)
EEPR
OM
(A
T24
C25
6)
IIC1 IIC2 IIC3 IIC4
IIC3
IIC4
OR4
Wired
-
OR
OR4
IIC2
KA752
7
0
7
4
HC14
Rese
t
Addr0,
WBE0,
OE, CS
Addr
.[1:
12],
WR,CS
,STRB
,
D
A
CK,CLK, Reset
Data[0:7]
Rx,Tx
Data[0:31
]
SDRAM
(HY57
V
6
5
1
6
2
0B
)
SDRAM
(HY57
V
6
4
1
6
2
0B
])
Addr
.[2:
13,22:23],
CLK,CKE,CS
,W
E
,
CAS
,RAS
,DQM
[0:3]
Data[0:31
]
FLASH
(29L
V16
0
B
)
FLASH
(A
T49
L
V16
0)
Addr
.[2:
21],
CS
,WE,
O
E
,
FlashDo
wn
RD
Y
,
DREQ,
IRQ
EN[0:
3
]
IRQ
Vide
o
Dec
oder
(VPX3
2
2
6
E)
X-tal
(20.
2
5
M
)
IIC2
3
D-Comb
Filte
r
L
VDS T
x
(THC63
L
VDM8
3R)
TX[0:2]
–
, TXC
–
8
RGB
HV
24
2
DOutClk
HD-II HD-II HD-II
J
e
pico
HV
RGB
24
3 2
YPb
P
r
J
e
pico
RGB out
test
V
,YC
3
MNT_
Out
J
e
pico
DOutClk
9
Data
[0:7
],
CLK
HD-II
VA
L
ID
IIC4
3
YCbCr
SDRAM
(HY57
V
6
4
3
2
2
0C)
SDRAM
(HY57
V
6
4
1
6
2
0B)
x4
Rear A
V
V,
L
R
3
Fr
ont A
V
V,
L
R
3
Rear S
YC
2
Fr
ont S
YC
2
A/V S
W
(CXA20
6
9
)
Comp_
1
YCbCr
3
Comp_
2
YCbCr
3
MSP4
4
4
0
Vide
o SW
(CXA21
8
1
)
Ext A
LR
2
IIC2
OR3
Sound
Pr
oc
(MSP4
4
4
0)
I2S
2
SIF
MNT_
O
u
t
LR
2
LR
2
CXA20
6
9
IIC4
I2S
Out
3
HD-II
HD-II
I2S
_In
SPDIF Re
v
.
(CS84
15A)
MUX
(74157)
MUX
(74157)
SPDIF Out
SPDIF In(D
VI)
SPDIF
In(D
VD)
IIC3
CPU
S
e
l_HD2
Sel
_
D
V
D
CPU
SPDIF In
SPDIF Out
uCom
(M30
6H3
)
IIC4
Rese
t
Rese
t
TMDS Rx
(HDCP)
Sil1
6
9
BSS8
3
BSS8
3
8
2
RX[0:
2
]
–
, RXC
–
DDC(I2C)
RGB
H,V
,
CLK
3
24
OR1 OR2
EEPR
OM
(A
T24
C02)
CPU
PD
I2C E
xt.
(82B7
1
5
)
Rese
t
EPLD1
(XC95
1
4
4
XL
)
E
P
L
D_JT
A
G
I2C_
Hub
[0:
1
]
Reset
Error
,E
m
p
h
4
IN2 IN3 IN4
IN1
OUT2
OUT1
OUT1
TV
IN2
IN3 IN4 IN1 IN2
IN4
IN5
HD2_E
XT
HD2_CHA
SDRAM I
/F
Host I
/F
Vide
o
Out
PWM, Cloc
k
Comp_
1
LR
2
Comp_
2
LR
2
RGB1
LR
2
NTSC
T
une
r
LPF
(8M)
LPF
(8M)
1
V
MNT_
O
u
t
A
T/NT
NTSC
V
IIC1
IIC2
A
TSC/NTSC T
uner
(TD
VB-H751P)
A
VSB
(LGDT31
0
2
)
RF
Jac
k
OSC (25M
)
2.5
V
Reg.
IF_A
GC
2
nd
IF
±
(6M)
SIF
MSP 44
40
T
uner B/D
PWM
modu
lator
(NSP6241B)
Digita
l
amp
.
(T
A5122)
A
udio
ADC
(CS5331)
LR
J
e
pico
RGB
HV
24
2
DOutClk
FPGA
[Decr
y
ption
]
Config
De
v
.
[EEPR
OM
]
10
Ser
ia
l
In
terf
ace
10
TP[0
:7],
TP_CL
K,
TP_v
a
lid
IIC2
IN1
RGB-IP
5
RGBHV
CM05
2
8
Switc
h
RGB2
LR
2