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Only for training and service purposes
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- 23 -
BLOCK DIAGRAM
1. Main
<
1
/
1
1
>
CO
M
P
O
N
E
N
T
RG
B
HDM
I1
,
HDM
I2
,
HDM
I3
R
ear
SC
A
R
T1
(A
V
1
)
S
ide
A
V
3
C
o
m
pos
it
e
, S-
V
id
e
o
TS
[
0
:7
]
CV
B
S
, L
/
R
SC
A
R
T2
(A
V
2
)
DDR
2
S
D
R
A
M
(6
4
M
B
y
te
)
HY
N
IX
IC7
0
0
NA
N
D
F
la
s
h
HY
N
IX
IC
4
0
4
L
V
DS
T
M
D
S
O
D
D[
1
0
b
it
]
60H
z
M
o
d
u
le
SP
D
IF
US
B
SP
D
IF
_
O
U
T
Di
g
it
a
l am
p
(N
T
P
30
00A
)
IC
6
0
0
RS
-2
3
2
C
T
M
D
S
351P
A
G
IC2
0
0
YP
b
P
rL
/
R
RG
B
, C
V
B
S
CV
B
S
DT
V
/
M
N
T
O
U
T
I2
S
24L
C
512
512K
b
it
IC
9
0
1
HDM
I4
Si
d
e
RG
B
,P
C
L
/
R
Tun er
(TDFV- G1 35D1)
TU3 00
TMD
S
[
0
:7
]
120H
z
m
o
d
u
le
74LVC541A(PW)
Buff er
I C400
CI Slot
(P400)
74LVC245A
Bi-Buffer
I C402
DA
T
A
[
0
:7
]
74LCX244MTC
Buff er
I C403,405, 406
Ad
d
re
s
s
[
0
:1
4
]
,C
T
R
L
s
ig
n
a
ls
TMD
S
[
0
:7
]
CV
B
S
Tun
er
Vo
ut
NLASB3157
I C500
LV
D
S
T
M
D
S
E
V
N[
1
0
b
it
]
L
V
DS
T
M
D
S
O
D
D[
1
0
b
it
]
Ho
s
t A
d
d
res
s
[
1
:1
6
]
H
o
st
D
a
ta
[
0
:15]
LP
F
D
D
R
2
D
a
ta
[
0
:15]
DDR
2
S
D
R
A
M
(64M
B
y
te
)
HY
N
IX
IC7
0
1
D
D
R
2
D
a
ta
[
16:
31]
D
D
R
2
A
d
d
re
ss[
0:
1
2
]
I2
C
MI
C
O
M
WT
6
1
P
8
IC
802
I2
C
M
A
X
3
2
3
2
CDR
IC
1
0
4
RX
TX
NLASB3157
I C101
TX
TX
AT2
4
C
1
6
A
N
16K
IC8
0
1
FLI
1
0
6
2
0
H
IC1
0
0
MSP4458G
I C603
S
IF,
S
C
AR
T
1
,2
L/
R
,AM
Au
d
io
Sw
it
c
h
in
g
L
R
I2
S
T
V
ou
t,
D
T
V
ou
t L
R
IC
9
0
4
UP
D
7
2
0
1
1
4
US
B
H
u
b
Bl
u
e
to
o
th
FR
C
IC
5
0
2
Содержание 32LG7000
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