LeCroy 1881M, Руководство пользователя, Страница: 20 / 38

1881M
Product Description
2-11 July 23, 1998
2.8 Readout
2.8.1 Single Read from Data Space
Reading of the data can be done using random read cycles, however, first the correct number of words to
read must be ascertained. Assuming Load Next Event has been used to select the desired event to read, the
first location of this buffer, the header word, must be read to find out how many words are in the event.
Bits <6:0> of the header word contain the word count for the event. This word count is the number of data
words plus one for the header word itself. With this information the correct number of words for the event
can be read by repeated reads to DSR0.
2.8.2 Block Transfer Read from Data Space
Block transfers are the preferred way to read data from the 1881M, and this is facilitated by the Load Next
Event function, CSR0<10>. A write to CSR0<10>, increments the internal read pointer by one and loads
CSR5 with the word count for that event. This can be done for an entire crate at one time using a
broadcast. A subsequent block read will transfer data until automatic decrementing of CSR5 reaches 0, the
end of the event's data. . When the unit is done reading out all the data for that event SS = 2. The first
word transferred is the header word.
2.9 FASTBUS Write to Data Memory
Although not pertinent to data acquisition, it is possible to write to the data memory via FASTBUS.
This may be desired for testing. For this purpose, the data memory appears as a 8192 x 32 bit word
RAM. Data may be written into this RAM using random, or broadcast modes. Block writes to data space
are not supported. Since the 1881M event manager is not managing this loading, the parity checking,
channel identification, and geographic address identification normally present in the data are not present
when read back.
2.10 Fast Clears
A fast clear can be applied any time during the fast clear window. This will cause the event just recorded
in the front end not to be buffered. The write page will not be incremented. The buffering situation will be
as though the cleared event never took place. This action requires a minimum time given in the
specification. This is the time starting from the beginning edge of the fast clear pulse until the module is
ready to accept another event. Fast clears can be applied either from the front panel input, by writing
CSR0<31>, which can of course be done using a broadcast write, or via a model 1810 CAT (TR0).
2.11 Allocation of Restricted Use Lines
Using CSR1, the 1881M can be enabled to accept Common, Fast Clear Window, and Fast Clear inputs on
the TR lines. In addition, during internal test mode the 1810 CAT can be used to control the magnitude of
the test pulse using the UR lines. These lines have been allocated to be compatible with the LeCroy model
1810 Calibration and Timing module facilitating distribution of these signals throughout a crate. The
assignments are:
TR0 - Fast Clear
TR1,2 - Gate (TR1 +, TR2 -)
TR3 - Test Pulse