
PPC600 Family Debugger | 3
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1989-2022
Lauterbach
Access Classes to Other Addressable Core and Peripheral Resources
Lock and tristate the debug port
Real-time memory access (non-intrusive)
Configure debugger according to target topology
Control pin 8 of debug connector
Assign core to TRACE32 instance
Configure driver strength of TCK pin
Set base address for on-chip peripherals
Implicitly use run-time memory access
Freeze timebase when core halted
Invalidate instruction cache before go/step
Disable interrupts while single stepping
Disable interrupts while HLL single stepping
Set MSR_IP value for breakpoints / SYStem.Up
Enable memory access safeguard
Configure memory access timing
Separate address spaces by space IDs
Disable JTAG stop on debug events
Use alternative software breakpoint instruction