Lauterbach MicroBlaze Debugger Скачать руководство пользователя страница 34 | Manualshive

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Lauterbach MicroBlaze Debugger Скачать руководство пользователя страница 34

MicroBlaze Debugger and Trace | 34

©

1989-2021

Lauterbach GmbH

TrOnchip Commands

TrOnchip.state

Display on-chip trigger window

Opens the

TrOnchip.state

window.

TrOnchip.RESet

Set on-chip trigger to default state

Sets the TrOnchip settings and trigger module to the default settings.

TrOnchip.CONVert

Adjust range breakpoint in on-chip resource

The on-chip breakpoints can only cover specific ranges. If a range cannot be programmed into the
breakpoint, it will automatically be converted into a single address breakpoint when this option is active. This
is the default. Otherwise an error message is generated.

Format:

TrOnchip.state

Format:

TrOnchip.RESet

Format:

TrOnchip.CONVert

[

ON

|

OFF

] (deprecated)

Use

Break.CONFIG.InexactAddress

instead

TrOnchip.CONVert ON

Break.Set 0x1000--0x17ff /Write

Break.Set 0x1001--0x17ff /Write

…

TrOnchip.CONVert OFF

Break.Set 0x1000--0x17ff /Write

Break.Set 0x1001--0x17ff /Write

; sets breakpoint at range

; 1000--17ff sets single breakpoint

; at address 1001

; sets breakpoint at range

; 1000--17ff

; gives an error message

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Содержание MicroBlaze Debugger

Страница 1: ...MANUAL Release 09 2021 MicroBlaze Debugger and Trace...

Страница 2: ...12 SYStem Up Errors 12 FAQ 12 Displaying MicroBlaze Core Configuration 13 CPU specific Implementations 14 Memory Accesses Causing Bus Errors 14 Breakpoints 15 Software Breakpoints 15 On chip Breakpoin...

Страница 3: ...CONFIG MDM DebugPort Set core to debug 32 SYStem CONFIG MDM RESet Reset MDM configuration 32 SYStem CONFIG MDM view Display MDM configuration 33 SYStem CONFIG MDM UserInst Set default user BSCAN port...

Страница 4: ...s for different configurations of the debugger T32Start is only available for Windows General Commands general_ref_ x pdf Alphabetic list of debug commands Architecture specific information Processor...

Страница 5: ...terbach TRACE32 infrastructure for software debugging over a single shared connection to the target board via Lauterbach hardware For more details see Integration for Xilinx Vivado int_vivado pdf NOTE...

Страница 6: ...Cable from the target while the target power is off 2 Connect the host system the TRACE32 hardware and the Debug Cable 3 Power ON the TRACE32 hardware 4 Start the TRACE32 software to load the debugger...

Страница 7: ...ware memecfx12lc stopandgo download bit The FPGA configuration can be done using Xilinx Vivado or its predecessor Xilinx iMPACT or the TRACE32 command JTAG PROGRAM or the old version of the command JT...

Страница 8: ...croBlaze processors select which one you want to debug 4 Attach to the target and enter debug mode using the multicore settings from above This command resets the CPU and enters debug mode After execu...

Страница 9: ...th cygdrive c By using the option CYGDRIVE TRACE32 internally converts this prefix to the correct syntax e g to c on windows hosts Refer for more information to Data LOAD Elf 6 Open the disassembly an...

Страница 10: ...vely use the following command in the TCL console assuming your MDM has the default instance name mdm_0 4 Connect an appropriate clock signal to the TRACE TRACE_CLOCK port and export the TRACE TRACE_D...

Страница 11: ...need to contain debug information It is recommended to compile MicroBlaze software with the GCC option g3 The option g creates debug info that does not work well with TRACE32 Also keep in mind that u...

Страница 12: ...olves rapidly and therefore regular updates of the debugger software are necessary Note that the software downloads on the LAUTERBACH website represent stable releases but are not necessarily the late...

Страница 13: ...ze Core Configuration As the Microblaze core is configurable the available debug features depend on the current core The configuration of the core can be displayed using the command per When pointing...

Страница 14: ...inuation of the program Therefore inside an exception handler MSR EIP 1 the debugger uses a different memory access method that preserves the correct system state but does not detect bus errors In thi...

Страница 15: ...are also referred to as hardware breakpoints in non Lauterbach terminology The following list gives an overview of the usage of the on chip breakpoints by TRACE32 ICD Instruction breakpoints stop the...

Страница 16: ...TRACE32 correctly for this configuration is The following breakpoint combinations are possible Software breakpoints On chip breakpoints Map BOnchip 0x0 0x0FFFFF Break Set 0x100000 Program Software Bre...

Страница 17: ...tor table pre loaded with the memory image must contain a breakpoint handler If all program memory is read only consider the use of OnChip breaks as alternative SYStem Option BrkVector Configures an a...

Страница 18: ...HLL single steps Useful to prevent interrupt disturbance during HLL single stepping SYStem Option LittleEndian Select little endian mode Selects endianness SYStem Option MMUSPACES Separate address spa...

Страница 19: ...register R1 R31 caches and UTLB NOTE SYStem Option MMUSPACES should not be set to ON if only one translation table is used on the target If a debug session requires space IDs you must observe the fol...

Страница 20: ...es STDIO via MDM UART Sample script for opening term window attached to MDM UART core Format SYStem Option DUALPORT ON OFF Format SYStem Option MDMSINGLELMB ON OFF OFF Use a separate LMB master for ea...

Страница 21: ...roBlaze Debugger and Trace 21 1989 2021Lauterbach GmbH To confirm if the MDM UART is enabled in your design open the peripheral window via the PER command and look for the section MDM UART Configurati...

Страница 22: ...register etc are named according to the convention in the MicroBlaze Processor Reference Guide and shown accordingly in the Register view window These names are also used in the disassembly views and...

Страница 23: ...of multiple cores in an FPGA design Instead of using the deprecated options the following sequence is recommended to attach to a specific core in an FPGA design Note that all the cores inside an FPGA...

Страница 24: ...and tristate the debug port Default OFF If the system is locked no access to the debug port will be performed by the debugger While locked the debug connector of the debugger is tristated The main int...

Страница 25: ...ormat SYStem MemAccess mode mode Denied Enable StopAndGo Denied No memory access is possible while the CPU is executing the program Enable CPU depre cated Accesses are performed via the MicroBlaze Deb...

Страница 26: ...of NoDebug Go Resets the target with debug mode enabled and prepares the CPU for debug mode entry After this command the CPU is in the system up mode and running Now the processor can be stopped with...

Страница 27: ...tristate mode Please note nTRST must have a pull up resistor on the target TCK can have a pull up or pull down resistor other trigger inputs need to be kept in inactive state Format SYStem CONFIG par...

Страница 28: ...This is the sum of the instruction register lengths of all TAPs between the TDI signal of the debugger and the core of interest TAPState default 7 Select DR Scan This is the state of the TAP controlle...

Страница 29: ...nstruction register length of Core A 3 bit Core B 5 bit Core D 6 bit SYStem CONFIG IRPRE 6 IR Core D SYStem CONFIG IRPOST 8 IR Core A B SYStem CONFIG DRPRE 1 DR Core D SYStem CONFIG DRPOST 2 DR Core A...

Страница 30: ...21Lauterbach GmbH TapStates 0 Exit2 DR 1 Exit1 DR 2 Shift DR 3 Pause DR 4 Select IR Scan 5 Update DR 6 Capture DR 7 Select DR Scan 8 Exit2 IR 9 Exit1 IR 10 Shift IR 11 Pause IR 12 Run Test Idle 13 Upd...

Страница 31: ...ore you have to assign the core_index and the chip_index for every core Usually the debugger does not need further information to access cores in non generic chips once the setup is correct Generic Ch...

Страница 32: ...dule MDM is to be debugged by the current GUI The first core connected to the MDM is always numbered 0 Connecting to the core will fail if the selected number exceeds the number of debug ports of the...

Страница 33: ...ails the debugger will try the other instructions Therefore it is only required that you set the correct instruction if you either have multiple MDM instances in your FPGA design and wish to select a...

Страница 34: ...be programmed into the breakpoint it will automatically be converted into a single address breakpoint when this option is active This is the default Otherwise an error message is generated Format TrO...

Страница 35: ...or breakpoint to a complex variable the on chip break resources of the CPU may be not powerful enough to cover the whole structure If the option TrOnchip VarCONVert is set to ON the breakpoint will au...

Страница 36: ...TaskPageTable task_magic task_id task_name space_id 0x0 cpu_specific_tables root The root argument can be used to specify a page table base address deviating from the default page table base address T...

Страница 37: ...the given process Specify one of the TaskPageTable arguments to choose the process you want In MMU based operating systems each process uses its own MMU translation table This command reads the table...

Страница 38: ...command reads the MMU translation table of the kernel and lists its address translation TaskPageTable task_magic task_id task_name space_id 0x0 Lists the MMU translation of the given process Specify o...

Страница 39: ...tion into the debugger internal static translation table if range or address have a space ID loads the translation table of the specified process else this command loads the table the CPU currently us...

Страница 40: ...software breakpoints Default OFF Enable this system option in order to optimize tracing of software breakpoints When hitting a software break earlier versions of MicroBlaze jump to a software break ha...

Страница 41: ...ntical with those used for debugging a MicroBlaze core Also ensure that the debugger is in SYStem down mode before configuring your FPGA Configuring the FPGA will break the communication link between...

Страница 42: ...at converts the PPC400 pinout to that of the 14 pin Xilinx JTAG connector which is listed below Signal Pin Pin Signal TDO 1 2 N C TDI 3 4 TRST N C 5 6 VCCS TCK 7 8 N C TMS 9 10 N C HALT 11 12 N C N C...

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