C2000 Debugger | 47
©
1989-2023
Lauterbach
SYStem.LOCK
Tristate the JTAG port
Default: OFF.
If the system is locked, no access to the JTAG port will be performed by the debugger. While locked the
JTAG connector of the debugger is tristated. The intention of the
SYStem.LOCK
command is, for example,
to give JTAG access to another tool. The process can also be automated, see
It must be ensured that the state of the TI DSP core JTAG state machine remains unchanged while the
system is locked. To ensure correct hand-over, the options
must be set properly. They define the TAP state and TCK level which is
selected when the debugger switches to tristate mode. Please note: nTRST must have a pull-up resistor on
the target.
RTCK
The JTAG clock is controlled by the RTCK signal (Returned TCK).
On some processor derivatives including an ARM core (e.g. OMAP)
there is the need to synchronize the processor clock and the JTAG clock.
In this case RTCK shall be selected. Synchronization is maintained,
because the debugger does not progress to the next TCK edge until after
an RTCK edge is received.
When RTCK is selected, the maximum reachable frequency is limited to
10 MHz. This limit can be changed by adding the frequency parameter. A
limitation is required that the JTAG clock speed cannot become higher than
the physical interface can manage.
SYStem.JtagClock RTCK 20MHz
ARTCK
Accelerated method to control the JTAG clock by the RTCK signal
(Accelerated Returned TCK). RTCK mode allows theoretical frequencies up
to 1/6 of the processor clock. For designs using a very low processor clock
we offer a different mode (ARTCK) which does not work as recommended
by ARM and might not work on all target systems. In ARTCK mode the
debugger uses a fixed JTAG frequency for TCK, independent of the RTCK
signal. This frequency must be specified by the user and has to be below 1/2
of the processor clock speed. The signal RTCK clocks TDI and TMS and
controls the sampling of TDO.
Format:
SYStem.LOCK
[
ON
|
OFF
]
Содержание C2000
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