6
HDMI Mezzanine Card – Revision B
User’s Guide
Figure 5. Conceptual Connection for Headers H1 to H12
J3 (HDMI Out)
H12, H11,
H10, H9
H8, H7,
H6, H5
H4, H3,
H2, H1
LatticeECP3
FPGA
TMDS
Equalizer
J2 (HDMI Input 2)
J1 (HDMI Input 1)
Figure 6. Example for Bypassing CEC, HPD, SDA, SCL Between J1 and J3
H12, H11,
H10, H9
H8, H7,
H6, H5
H4, H3,
H2, H1
LatticeECP3
FPGA
TMDS
Equalizer
J3 (HDMI Out)
J2 (HDMI Input 2)
J1 (HDMI Input 1)
Technical Support Assistance
Hotline:
1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail:
Internet:
Revision History
Date
Version
Change Summary
September 2010
01.0
Initial release.
September 2012
01.1
Added Appendix B. Hardware Variants.
Updated document with new corporate logo.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at
. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
