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HDMI Mezzanine Card – Revision B
User’s Guide
Appendix B. Hardware Variants
Early versions of the HDMI Mezzanine Card Revision B were produced with U3 (STMicroelectronics STDVE001A
Adaptive single 3.4 Gbps TMDS/HDMI signal equalizer) populated. On the current version of the HDMI Mezzanine
Card Revision B, U3 is not populated.
To receive HDMI/DVI input when U3 is unpopulated:
• Connect the HDMI/DVI source using J2.
• Install a shunt between pin 2 and pin 3 of header H13 to route J2 HDMI/DVI signals to the FPGA via the Mezza-
nine connector.
On the current version of the board, the following additional changes were made:
• To support the Extended Display Identification Data (EDID) via the I
2
C interface of the FPGA, two modification
wires are installed in the following locations on the new HDMI Mezzanine Card Revision B:
– R15 (pad nearest U3) to R12 (pad nearest U3)
– R14 (pad nearest U3) to R11 (pad nearest U3)
These wires bridge the I
2
C bus around vacant U3.
• The resistors R2, R3, R6 and R7 are not populated (to reduce I
2
C bus pull-up strength).
• The resistors R71 and R58 are not populated (to correct a pull-down contention).
