Lattice CrossLink-NX PCIe, Руководство пользователя

Страница: 36 / 46

CrossLink-NX PCIe Bridge Board Basic Demo
User Guide
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal .
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36 FPGA-UG-02145-1.0
The interactive 7 Segment Control page demonstration illustrates that a functional PCI Express communications path
exists between the application and driver software on the CPU and the FPGA IP.
Table 5.3. Memory Data and Corresponding 7 Segment Display Values
Memory Data 7 Segment Display Value
3F 0
06 1
5B 2
4F 3
66 4
6D 5
7D 6
07 7
7F 8
6F 9
77 A
7C B
39 C
5E D
7B E
71 F
Go to the Bar Memory Read Write tab, select either the 8-bit, 16-bit, or 32-bit radio button. In write address, enter 0x0
and one by one enter the values from
Table 5.3 in data edit box and click the Write button. The first byte controls the
first digit of the display, the second byte controls the second digit of the display, and the third byte controls the third
digit of the display. After each write operation you can cross verify that the correct segments in Segment Display tab
and in the 7 Segment Display of the board display the correct number.