18
POWR607/6AT6 Evaluation Board
Pulse Stretch Circuit
The pulse stretch circuit (Schematic Sheet 4 of 5) produces a ~40ms period pulse so watchdog timer interrupt out-
puts are visible to the eye. When active, amber LED (D11) blinks. The actual output pulse generated by the
POWR607 is about 6 µs.
Push-button Switches
The board has two momentary push-button switches (SW2 and SW3) to support the pre-loaded processor support
demo. SW2 is tied to a POWR607 input pin (IN1) which asserts the Reset input. SW3 is tied to a POWR607 input
pin (IN2) which asserts the watchdog trigger (WD_Trig) input. You may use SW2/SW3 for user-defined inputs for
your own custom POWR607 designs.
Modifying the POWR607/6AT6 Evaluation Board
The POWR607/6AT6 Evaluation Board provides landing areas for additional circuits to support the following func-
tions:
• Additional voltage supervisor input circuits
• SMD and thru-hole prototyping areas on top and bottom
• Measure power-down current draw of the POWR607 device
• Bypass devices in the JTAG programming chain
• Powering the board with an external 5 V supply
• Programming the board with a JTAG cable
• Interfacing to the PAC-Designer I
2
C Utility software for the POWR6AT6 Power Manager II
Note: Modifying your board requires good e
lectronics handling and PCB fabrication techniques to avoid damage.
Adding Support for a JTAG Cable and/or I
2
C Communications
This section describes how to modify the POWR607/6AT6 evaluation board to use a JTAG cable for JTAG program-
ming and/or I
2
C communications. The JTAG header interface is required if your PC does not provide a USB port
interface and you wish to reprogram the board. The I
2
C header interface is required to communicate with the PAC-
Designer POWR6AT6 I
2
C Utility program.
To modify the evaluation board to support a JTAG cable:
1. Remove R20, R35, R45 and R58 (Schematic Sheet 2 of 6).
2. Install R28, R29, R27, Q3 and Q2 (Schematic Sheet 5 of 6).
3. Install an 8-pin header at location J3 - JTAG Interface (Schematic Sheet 5 of 6).
To modify the evaluation board to support I
2
C communications:
1. Remove R59 and R70 (Schematic Sheet 2 of 6).
2. Install an 8-pin header at location J2 - I
2
C Interface (Schematic Sheet 5 of 6).
