MachXO5-NX Development Board
Evaluation Board User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
44
FPGA-EB-02052-0.90
Figure A.7. High Speed Header (BANK5/6)
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
NOTE : PLACE ALL THE TERMINATION
RESISTORS ON TOP SIDE AND CLOSE
TO THE U3
LVDS RX TERMINATION RESISTORS
Note :
1) Match length within pair as well as other pairs with +/- 5% tolerence
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)All the power rails should be capable of carrying 1A current
R
X
C
o
nn
e
ct
o
r2
Note : Speed of the bus, < 2.5ps skew for pairs and
across the bus, traces should be 100 Ohms
Trace match LVDSI* pins between P and N channels as
well as individual pairs.
R
X
C
o
nn
e
ct
o
r1
CrossLink Headers
1%
CH0_DCK_P
CH0_DCK_N
CH0_DATA0_N
CH0_DATA0_P
CH0_DATA1_P
CH0_DATA1_N
CH2_DATA1_N
CH2_DATA1_P
CH1_DCK_P
CH1_DCK_N
CH0_DATA3_P
CH0_DATA3_N
CH0_DATA2_N
CH0_DATA2_P
CH1_DATA0_N
CH1_DATA1_P
CH1_DATA0_P
CH1_DATA1_N
CH1_DATA2_N
CH1_DATA2_P
CH2_DATA0_P
CH2_DATA0_N
CH2_DCK_N
CH2_DCK_P
CH1_DATA3_N
CH1_DATA3_P
CH3_DATA1_N
CH3_DATA1_P
CH3_DCK_N
CH3_DCK_P
CH3_DATA0_N
CH3_DATA0_P
FX_MOSI
FX_SN
FX_SCLK
FX_MISO
CH1_DCK_P
CH1_DCK_N
CH1_DATA0_P
CH3_DATA0_N
CH1_DATA0_N
CH1_DATA2_P
FX_RESETN
CH1_DATA2_N
CH3_DCK_N
CH1_DATA3_N
CH1_DATA3_P
CH1_DATA1_N
CH3_DATA0_P
CH1_DATA1_P
CH3_DATA1_N
CH3_DATA1_P
CH3_DCK_P
CH0_DATA2_P
CH0_DATA1_P
CH0_DCK_P
CH0_DCK_N
CH0_DATA0_P
CH0_DATA0_N
CH0_DATA2_N
CH2_DATA0_P
CH2_DATA0_N
CH2_DCK_P
CH2_DCK_N
CH0_DATA1_N
CH0_DATA3_P
CH0_DATA3_N
CH2_DATA1_P
CH2_DATA1_N
FX_RESETN
SDA2
SCL2
SDA1
SCL1
SCL2
SDA2
SCL1
SDA1
FX_MOSI
FX_MISO
FX_SN
FX_SCLK
SGMII_MDIO_DATA
SGMII_MD1_N
SGMII_MD2_P
SGMII_MD1_P
SGMII_MD3_P
SGMII_MD3_N
SGMII_MD0_P
SGMII_MD0_N
SGMII_MD2_N
SGMII_INT
SGMII_PHY_SIP
SGMII_PHY_SIN
SGMII_CLK_OUT
SGMII_MDIO_CLK
SGMII_RST_N
SGMII_PHY_SOP
SGMII_PHY_SON
SGMII_PHY_COP
SGMII_PHY_CON
SGMII_LED2
SGMII_LED1
SGMII_LED0
SGMII_XO
SGMII_XI
SGMII_XO
SGMII_XI
SGMII_MD1_N
SGMII_MD2_P
SGMII_MD1_P
SGMII_MD3_N
SGMII_MD3_P
SGMII_MD2_N
SGMII_MD0_P
SGMII_MD0_N
SGMII_LED0
SGMII_LED1
SGMII_LED2
DPHY0_FSYNC
DPHY0_CKP
DPHY0_CKN
DPHY0_DP0
DPHY0_DN0
DPHY0_DP1
DPHY0_DN1
DPHY0_DP2
DPHY0_DN2
DPHY0_DP3
DPHY0_DN3
DPHY0_SDA
DPHY0_SCL
DPHY0_CLK
DPHY0_RST
DPHY0_CKP
DPHY0_CKN
SGMII_FPGA_CLKP
SGMII_FPGA_CLKN
SGMII_PHY_COP
SGMII_PHY_CON
SGMII_PHY_SOP
SGMII_PHY_SON
SGMII_FPGA_RXP
SGMII_FPGA_RXN
SGMII_FPGA_TXP
SGMII_FPGA_TXN
SGMII_PHY_SIP
SGMII_PHY_SIN
SDA1
SDA2
SCL1
SCL2
FX_SN
FX_MOSI
FX_MISO
FX_SCLK
FX_RESETN
DPHY0_DP3
DPHY0_DN3
DPHY0_DP1
DPHY0_DN1
DPHY0_DP0
DPHY0_DN0
DPHY0_DP2
DPHY0_DN2
CH1_DCK_P
CH1_DCK_N
CH3_DCK_N
CH3_DCK_P
CH1_DATA1_N
CH1_DATA1_P
CH1_DATA3_P
CH1_DATA3_N
CH1_DATA0_N
CH1_DATA0_P
CH1_DATA2_P
CH1_DATA2_N
SGMII_FPGA_CLKP
SGMII_FPGA_CLKN
SGMII_FPGA_RXP
SGMII_FPGA_RXN
SGMII_FPGA_TXP
SGMII_FPGA_TXN
CH0_DCK_P
CH0_DCK_N
CH2_DCK_P
CH2_DCK_N
CH0_DATA0_N
CH0_DATA0_P
CH0_DATA2_P
CH0_DATA2_N
CH0_DATA1_P
CH0_DATA1_N
CH0_DATA3_N
CH0_DATA3_P
CH2_DATA0_P
CH2_DATA0_N
CH2_DATA1_N
CH2_DATA1_P
CH3_DATA0_N
CH3_DATA0_P
CH3_DATA1_P
CH3_DATA1_N
SGMII_INT
SGMII_MDIO_DATA
SGMII_MDIO_CLK
SGMII_RST_N
DPHY0_SDA
DPHY0_SCL
DPHY0_FSYNC
DPHY0_CLK
DPHY0_RST
SGMII_CLK_OUT
+12V
+12V
+1.8V
+12V
+3.3V
+5.0V
+12V
+3.3V
+5.0V
+1.8V
+12V
+12V
+3.3V +1.8V
+5.0V +3.3V +1.8V
+5.0V
VCCIO5
VCCIO6
SGMII_VDDIO
SGMII_VDDIO
SGMII_PHY_D1V8
+2.5V
SGMII_VDDIO
+2.5V
+3.3V
+3.3V
+3.3V
VCCIO5
VCCIO6
VRAM
CVDD
+2.8V
VCCA_1V_PHY
+1.8V
+1.0V
VRAM
VCCA_1V_PHY
+2.5V
SGMII_PHY_D1V8
SGMII_VDDIO
SDA1
[8]
SDA2
[8]
SCL2
[8]
SCL1
[8]
FX_MOSI
[8]
FX_SN
[8]
FX_SCLK
[8]
FX_MISO
[8]
FX_RESETN
[8]
SGMII_INT
[8]
SGMII_MDIO_DATA
[8]
SGMII_MDIO_CLK
[8]
SGMII_RST_N
[8]
DPHY0_SDA
[9]
DPHY0_SCL
[9]
DPHY0_CLK
[9]
DPHY0_FSYNC
[9]
DPHY0_RST
[9]
SGMII_CLK_OUT
[8]
Date:
Size
Schematic Rev
o f
Sheet
Title
Lattice Semiconductor Applications
Email: [email protected]
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
1.0
MachXO5-NX Development Board
C
7
11
Thursday, January 13, 2022
A
High Speed Heads(BANK5/6)
Date:
Size
Schematic Rev
o f
Sheet
Title
Lattice Semiconductor Applications
Email: [email protected]
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
1.0
MachXO5-NX Development Board
C
7
11
Thursday, January 13, 2022
A
High Speed Heads(BANK5/6)
Date:
Size
Schematic Rev
o f
Sheet
Title
Lattice Semiconductor Applications
Email: [email protected]
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
1.0
MachXO5-NX Development Board
C
7
11
Thursday, January 13, 2022
A
High Speed Heads(BANK5/6)
D13
Red
R38
2.2K
DNI
C146 100nF
C181
1uF
R56
100
DNI
C175
1uF
C158
1uF
R54
100
DNI
R49
100
DNI
C18
18pF
C147 100nF
R53
100
DNI
MachXO5-NX
U3F
VCCIO5
T12
VCCIO5
V14
PB48B/ ADC_CN14/BDQ42
N12
PB48A/ ADC_CP14/BDQ42
N13
PB52A/ ADC_CP11/BDQ54
P13
PB40B/ COMP1IN/PCLKC5_0/BDQ42
R11
PB52B/ ADC_CN11/BDQ54
R13
PB58B/ PCLKC5_3/LRC_GPLL0T_MFGOUT2/BDQ54
R14
PB40A/ COMP1IP/PCLKT5_0/BDQ42
T11
PB50B/ COMP3IN/BDQ54
T13
PB58A/ PCLKT5_3/LRC_GPLL0T_MFGOUT1/BDQ54
T14
PB38B/ ADC_CN4/BDQ42
U11
PB44B/ COMP2IN/BDQ42
U12
PB50A/ COMP3IP/BDQ54
U13
PB56B/ ADC_CN15/BDQ54
U14
PB38A/ VREF5_1/ADC_CP4/BDQ42
V11
PB44A/ COMP2IP/BDQ42
V12
PB56A/ ADC_CP15/BDQ54
V13
PB42B/ PCLKC5_1/ADC_CN8/BDQSN42
W11
PB46B/ PCLKC5_2/ADC_CN13/BDQ42
W12
PB54B/ ADC_CN12/BDQSN54
W13
PB60B/ LRC_GPLL0C_IN/VREF5_2/ATB_SENSE/BDQ54
W14
PB42A/ PCLKT5_1/ADC_CP8/BDQS42
Y11
PB46A/ PCLKT5_2/ADC_CP13/BDQ42
Y12
PB54A/ ADC_CP12/BDQS54
Y13
PB60A/ LRC_GPLL0T_IN/ATB_FORCE/BDQ54
Y14
C184
0.1uF
Q2
MMBT3904
FB12
MPZ1005S121CT000
C182
0.1uF
R158
1M Ohm
C159
1uF
R89
100
R166
1K
DP83867ERGZT
U7
TX_D3
25
TX_D2
26
TX_D1/SGMII_SIP
27
TX_D0/SGMII_SIN
28
GTX_CLK
29
VDDIO
30
VDD1P0
31
RX_CLK
32
RX_D0/SGMII_COP
33
RX_D1/SGMII_CON
34
RX_D2/SGMII_SOP
35
RX_D3/SGMII_SON
36
TX_CTRL
37
RX_CTRL
38
GPIO_0
39
GPIO_1
40
VDDIO
41
VDD1P0
42
RESET
43
INT/PWDN
44
LED_2
45
LED_1
46
LED_0
47
VDDA1P8
48
TD_P_A
1
TD_M_A
2
VDDA2P5
3
TD_P_B
4
TD_M_B
5
VDD1P0
6
TD_P_C
7
TD_M_C
8
VDDA2P5
9
TD_P_D
10
TD_M_D
11
RBIAS
12
VDDA1P8
13
XO
14
XI
15
MDC
16
MDIO
17
CLK_OUT
18
VDDIO
19
JTAG_CLK
20
JTAG_TDO
21
JTAG_TMS
22
JTAG_TDI
23
VDD1P0
24
E
P
A
D
49
C183
0.1uF
R205
100
C162
0.1uF
C149 100nF
C160
1uF
C44
0.1uF
JP3
PHY_PD
1
2
R57
100
DNI
C166
10uF
C24
100nF
C43
0.1uF
R219
2.2K
C163
0.1uF
C161
1uF
R77
2.2K
C167
1uF
C148 100nF
R60
100
DNI
FB1
MPZ1005S121CT000
U5
Hirose - FX12 - 40 Pos
DNI
CH1_DCK_P
1
CH1_DCK_N
2
GND
3
CH1_DATA0_P
4
CH1_DATA0_N
5
GND
6
CH1_DATA2_P
7
CH1_DATA2_N
8
GND
9
SN
10
SCLK
11
PWR_12_0V
12
SDA1
13
SCL1
14
GND
15
CH3_DATA0_P
16
CH3_DATA0_N
17
GND
18
CH3_DCK_P
19
CH3_DCK_N
20
PWR_12V
21
RESETN
22
PWR_5-0V
23
CH1_DATA1_P
24
CH1_DATA1_N
25
PWR_3-3V
26
CH1_DATA3_P
27
CH1_DATA3_N
28
PWR_1-8V
29
MOSI
30
MISO
31
PWR_1-8V
32
GND
33
GND
34
PWR_3-3V
35
CH3_DATA1_P
36
CH3_DATA1_N
37
PWR_5-0V
38
SDA
39
SCL
40
Shield1
41
Shield2
42
Shield3
43
Shield4
44
Shield5
45
Shield6
46
R61
100
DNI
R220
2.2K
C26
100nF
C176
0.1uF
C168
1uF
R76
2.2K
C164
0.1uF
C157
10uF
C22
100nF
R221
2.2K
R167
1K
C177
0.1uF
R124
10K
C169
10uF
R64
100
DNI
R32
11K
C150 100nF
R52
100
DNI
C21
100nF
R59
100
DNI
D15
Red
C165
0.1uF
C170
0.1uF
C25
100nF
R51
100
DNI
MachXO5-NX
U3G
VCCIO6
T9
VCCIO6
V8
PB2A/ VREF6_1/BDQ6
N8
PB10A/ CDR_RXP1/ADC_CP3/BDQ6
N9
PB14A/ CDR0_TESTP/ADC_CP5/BDQ18
N10
PB36A/ BDQ18
N11
PB2B/ BDQ6
P8
PB10B/ CDR_RXN1/ADC_CN3/BDQ6
P9
PB14B/ CDR0_TESTN/ADC_CN5/BDQ18
P10
PB36B/ VREF6_2/BDQ18
P11
PB16A/ CDR1_TESTP/ADC_CP7/BDQ18
R10
PB4A/ BDQ6
T8
PB16B/ CDR1_TESTN/ADC_CN7/BDQ18
T10
PB4B/ BDQ6
U8
PB12A/ PCLKT6_2/ADC_CP2/COMP3P/BDQ6
U9
PB32A/ ADC_CP9/BDQ18
U10
PB12B/ PCLKC6_2/ADC_CN2/COMP3N/BDQ6
V9
PB32B/ ADC_CN9/BDQ18
V10
PB6A/ PCLKT6_0/CDR_RXP0/ADC_CP0/COMP1P/BDQS6
W7
PB8A/ PCLKT6_1/ADC_CP1/COMP2P/BDQ6
W8
PB18A/ ADC_CP6/BDQS18
W9
PB34A/ PCLKT6_3/ADC_CP10/BDQ18
W10
PB6B/ PCLKC6_0/CDR_RXN0/ADC_CN0/COMP1N/BDQSN6
Y7
PB8B/ PCLKC6_1/ADC_CN1/COMP2N/BDQ6
Y8
PB18B/ ADC_CN6/BDQSN18
Y9
PB34B/ PCLKC6_3/ADC_CN10/BDQ18
Y10
C151 100nF
C23
100nF
D14
Red
C39
10uF
R63
100
DNI
R68
0
DNI
R129
10K
C171
0.1uF
Q4
MMBT3904
J27
24580403
NC1
1
CLK_N
2
CLK_P
3
DGND
4
DATA3_N
5
DATA3_P
6
DGND
7
DATA1_N
8
DATA1_P
9
DGND
10
DATA0_N
11
DATA0_P
12
DGND
13
DATA2_N
14
DATA2_P
15
DGND
16
AF_GND
17
AF_VDD2V8
18
NC2
19
MCLK
20
NC3
21
SDA
22
SCL
23
RESET
24
VDD1.05V
25
DVDD1V8
26
DGND
27
AGND
28
AVDD2V8
29
AGND
30
R67
0
DNI
C185
1uF
C40
0.1uF
C178
10uF
J14
7498111001-RJ45
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
G
R
O
U
N
D
1
S
1
G
R
O
U
N
D
2
S
2
R36
100
R75
22
U4
Hirose - FX12 - 40 Pos
DNI
CH0_DCK_P
1
CH0_DCK_N
2
GND
3
CH0_DATA0_P
4
CH0_DATA0_N
5
GND
6
CH0_DATA2_P
7
CH0_DATA2_N
8
GND
9
SN
10
SCLK
11
PWR_12V
12
SDA1
13
SCL1
14
GND
15
CH2_DATA0_P
16
CH2_DATA0_N
17
GND
18
CH2_DCK_P
19
CH2_DCK_N
20
PWR_12-0V
21
RESETN
22
PWR_5-0V
23
CH0_DATA1_P
24
CH0_DATA1_N
25
PWR_3-3V
26
CH0_DATA3_P
27
CH0_DATA3_N
28
PWR_1-8V
29
MOSI
30
MISO
31
PWR_1-8V
32
GND
33
GND
34
PWR_3-3V
35
CH2_DATA1_P
36
CH2_DATA1_N
37
PWR_5-0V
38
SDA
39
SCL
40
Shield1
41
Shield2
42
Shield3
43
Shield4
44
Shield5
45
Shield6
46
C27
100nF
C173
1uF
Q3
MMBT3904
X3
25 MHz
ABM3-25
1
2
R58
100
DNI
R65
2.49K
R165
1K
C19
18pF
R50
100
DNI
C41
0.1uF
C156
10uF
C179
1uF
C172
10uF
R233
4.7k
R55
100
DNI
FB6
MPZ1005S121CT000
FB10
MPZ1005S121CT000
R66
2.49K
R62
100
DNI
C42
10uF
C28
18pF
C180
10uF
R203
100
C174
10uF
C20
100nF
R234
4.7k
Содержание MachXO5-NX Development Kit
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