Lattice Semiconductor MachXO2 Series, Руководство пользователя

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18
MachXO2 Breakout Board
Evaluation Kit User’s Guide
Appendix A. Schematics
Note: The schematics are drawn using the MachXO2-1200ZE device. Please consult Tables 3 through 6 for -1200
and -7000HE pin name and bank synonyms. Pin numbers are correct for either device.
Figure 7. Block Diagram
5 5
4 4
3 3
2 2
1 1
D
D
C
C
B
B
A
A
FPGA
Power from USB 5V
BANK 3
BANK 1
BANK 0
BANK 2
LCMXO2-7000HE-4TG144C or LCMXO2-1200ZE-1TG144C
HEADER
HEADER
HEADER
I/Os + SPI
I/Os
I/Os
HEADER
I/Os + I2C
JTAG
RS232
USB CONNECTOR
USB to JTAG / RS232
LEDS(1-8)
Ti
tl
e
Si
z
e
Do
c
u
m
e
n
t Nu
m
b
e
r
Da
te
:
S
h
e
e
t
of
AXELSYS
Lat
ti
c
e MachX
O
2 1200ZE
B
reakout
B
oar
d -
B
lock D
iagr
am
B
15
Thur
sday,
A
p
ri
l 21,
2011
Ti
tl
e
Si
z
e
Do
c
u
m
e
n
t Nu
m
b
e
r
Da
te
:
S
h
e
e
t
of
AXELSYS
Lat
ti
c
e MachX
O
2 1200ZE
B
reakout
B
oar
d -
B
lock D
iagr
am
B
15
Thur
sday,
A
p
ri
l 21,
2011
Ti
tl
e
Si
z
e
Do
c
u
m
e
n
t Nu
m
b
e
r
Re
v
Da
te
:
S
h
e
e
t
of
AXELSYS
LCMXO2-7000HE-B-EVN or LCMXO2-1200ZE-B-EVN
A
Lat
ti
c
e MachX
O
2 1200ZE
B
reakout
B
oar
d -
B
lock D
iagr
am
B
15
Thur
sday,
A
p
ri
l 21,
2011