MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-202
2
Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02051-2.3
7
Two 2 × 20 Header
Landings (J3, J5)
Two 2 × 20
Header
Landings
(J2, J4)
MachXO2
PLD (U3)
FTDI USB to
UART/FIFOIC
(U1)
JTAG Header
Landing (J1)
USB Mini-B
Socket (J7)
Power LED
(PWR_ON)
Power/GNDTest
Points (TP1, TP2, TP3)
4 × 15 60-Hole
Prototype Array (J6)
LED Array (J4)
Figure 2.1. MachXO2 Breakout Board, Top Side