9
LatticeECP2M PCI Express x4
Lattice Semiconductor
Evaluation Board User’s Guide
separate output frequencies from a single input reference frequency. PAC-Designer
®
software (available from the
Lattice web site at www.latticesemi.com/pacdesigner) is used to program the ispClock features.
ispClock supports reference clocks in the range of 10 to 320 MHz. The duty cycle of the clock source need not be
50%; the only requirement is that both the HIGH and LOW times of this signal must be 1.25 ns or longer. The fol-
lowing standards are supported with either minimal or no external components: LVTTL, LVCMOS, SSTL2, SSTL3,
HSTL, LVDS and LVPECL.
When the ispClock5620A is in a LOCKED state, the LOCK output pin goes LOW. The LOCK
N
pins are connected
to amber LED D13 and will illuminate when the LOCK
N
pin goes low. The lock detector has two operating modes:
phase lock mode and frequency lock mode. In phase lock mode, the LOCK signal is asserted if the phases of the
reference and feedback signals match, whereas in frequency lock mode the LOCK signal is asserted when the fre-
quencies of the feedback and reference signals match.
U2 is controlled by SW4 or from a predefined connection to U1 (LatticeECP2M). The DIP switch controls the isp-
Clock device. The reference clock selection and device reset is controlled using the switches. The switches control-
ling the ispClock outputs can be synchronously controlled by the SGATE output on a bank-by-bank basis or tri-
stated on an output-by-output basis using the OEXb and OEYb inputs. All outputs may be tri-stated by bringing the
GOEb input high.
The VCCO voltage is board-connected to 2.5V or 3.3V based on the on-board connection of FB21 or FB22.
The output clocks of U2 are routed to devices to provide system level clocking. These pre-defined board clocks are
routed to input LatticeECP2M input clock pins for SERDES reference clocks, primary clocks, PLL inputs and DLL
inputs as well as connection to an SMA (J34). This SMA is 50-ohm terminated for off-board interconnection to test
equipment.
A clock input to the ispClock device can be provided from the PCI Express edge fingers. This is accomplished by
configuring the on-board resistor jumpers R79 and R80 (see Appendix A, Figure 9).
SERDES
(see Appendix A, Figure 9)
SERDES Reference Clock
The 50-ohm terminated SMA connectors are provided to supply reference clocks directly to the LatticeECP2M
device from the ispClock management device. This device drives clocks to both SERDES quads via 100-ohm
LVDS signaling. On-board clock oscillators mentioned in the previous sections can be chosen to drive the same
SERDES reference clocks. The board can also be provisioned to source the clock from the PCI Express edge fin-
gers directly to the SERDES REFCLK pins.
SERDES Channels
Note: Surface Mounted SMA Connections are only available for the LFE2M50E-FF672 device.
(see Appendix A, Figure 9)
DC coupled top-mounted SMA connectors connect to the three SERDES Tx and Rx channels of the L-Quad SER-
DES. These pins are directly coupled to the designated SMA connector creating a path for both input and output
differential data.
