iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
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.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02007-1.1
23
Figure A.2. iCE40UP5K FPGA A - Display
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
LATTICE SEMICONDUCTOR CORPORATION CONFIDENTIAL
iCE40 UltraPlus Mobile Development Platform
VCC Sense Resistors - 1 Ohm 0603
Add test points on both sides
Note:
Place close
to DUT
Note:
Place close
to DUT
DONE_A
Function Mapping from iCE40UP to Board
Note:
Place close
to DUT
Note:
Place close
to DUT
Note:
Place close
to DUT
To Interconnects Page
0201
To Display Connect Page
Place close to ICE40
Note :
1) Match length within pair as well as other pairs with +/- 5% tolerence
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)All the power rails should be capable of carrying 1A current
4)Place MIPI TX resistor network as close to bank 1 as possible.
Trace match *HS* P & N channels as well as individual pairs.
Minimize routing and trace match *LP* signals..
VCC1V2
VCC2V5
VCC3V3
VCC3V3
VCC1V2
VCC_iCE_A
VCCPLL_IN_A
VPP2V5_A
VCCIO0_iCE_A
SPIVCCIO1_iCE_A
VCCIO2_iCE_A
VCC_iCE_A
VPP2V5_A
VCCPLL_IN_A
SPIVCCIO1_iCE_A
VCCIO2_iCE_A
SPIVCCIO1_iCE_A
VCCIO0_iCE_A
VCC3V3
iCE_SS_A
{6}
CDONE
{3,4,5,6,11}
iCE_SCK_A
{6}
iCE_SI_A
{6}
iCE_SO_A
{6}
DSI_D0N
{7}
DSI_CLKP
{7}
DSI_CLKN
{7}
DSI_D0P
{7}
SPARE_A1
{7,13}
SPARE_A2
{7,13}
SPARE_A0
{7,13}
OSC_CLK
{3,4,5,8,10,13}
UART_TX
{3,4,5,6,10,13}
UART_RX
{3,4,5,6,10,13}
proc_cs
{3,4,5,6,10}
proc_intr
{3,4,5,6,10}
CRSTb
{3,4,5,6,10,11,13}
I2S_SD_mic7
{3,8}
Title
Size
Document Number
Rev
Date:
Sheet
of
D
iCE40UP5K FPGA A - Display
B
2
14
Friday, November 03, 2017
Title
Size
Document Number
Rev
Date:
Sheet
of
D
iCE40UP5K FPGA A - Display
B
2
14
Friday, November 03, 2017
Title
Size
Document Number
Rev
Date:
Sheet
of
D
iCE40UP5K FPGA A - Display
B
2
14
Friday, November 03, 2017
C13
0.1u
C3
1u
30
R36
R0201
5%
R178
1
C8
0.1u
R2
2k2
R19
0
C5
0.1u
TP31
1K
R38
5%
R0201
J17
iCEA Control
2
4
6
8
10
1
3
5
7
9
R15
0
C10
0.1u
D1
GREEN
2
1
R180
1
30
R72
R0201
5%
30
R33
R0201
5%
R142
0
DNI
TP1
J31
CON24A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R1
100
C2
0.1u
R141
0
R143
0
DNI
C9
10n
C14
1u
R182
1
1K
R71
5%
R0201
TP26
TP52
TP29
TP28
TP27
TP2
R179
1
Bank2
Bank1
Bank0
iCEUP5K-WLCSP30
iCE5UP5K-WLCSP30
U1
IOB_0A
E5
IOB_2A
D5
IOB_3B_G6
F5
IOB_9B
E4
IOB_10A
C3
IOB_11B_G5
F4
CRESET_B
F3
IOB_12A_G4_CDONE
D3
IOB_13B
E3
IOB_24A
B1
IOB_25B_G3
F2
IOB_32A_SPI_SO
F1
IOB_33B_SPI_SI
E1
IOB_34A_SPI_SCK
D1
IOB_35B_SPI_SS
C1
VCCPLL
B2
IOT_36B
A1
IOT_37A
A2
IOT_46B_G0
B3
IOT_47A
A4
RGB2
A5
RGB1
B5
RGB0
C5
G
N
D
B
4
G
N
D
E
2
VCC
C2
VCCIO_0
A3
SPI_VCCIO1
D2
VCCIO_2
C4
VPP_2V5
D4
C7
10u
1K
R34
5%
R0201
TP3
30
R46
R0201
5%
C12
10n
C6
10n
1K
R39
5%
R0201
TP50
C1
10n
TP30
C11
1u
R183
1
R181
1
C4
1u
TP51
VCCPLL_A
CDONE_A
CDONE
iCE_SS_A
iCE_SCK_A
iCE_SI_A
iCE_SO_A
VCCPLL_A
iCE_SS_A
iCE_SCK_A
iCE_SI_A
iCE_SO_A
UART_TX_A
UART_RX_A
OSC_CLK_A
CDONE_A
CRSTb_A
proc_cs_A
SPARE_A0
SPARE_A1
SPARE_A2
DSI_HS_CLKP
DSI_HS_D0P
proc_intr_A
DSI_HS_D0N
DSI_HS_CLKN
DSI_LP_CLKP
DSI_LP_CLKN
DSI_LP_D0P
DSI_LP_D0N
DSI_HS_D0P
DSI_HS_D0N
DSI_HS_CLKP
DSI_HS_CLKN
DSI_D0P
DSI_CLKN
DSI_LP_D0P
DSI_LP_D0N
DSI_LP_CLKP
DSI_LP_CLKN
DSI_D0N
DSI_CLKP
SPARE_A0
SPARE_A1
SPARE_A2
OSC_CLK_A
UART_TX_A
UART_RX_A
proc_cs_A
proc_intr_A
UART_TX_A
UART_RX_A
OSC_CLK_A
proc_cs_A
iCE_SS_A
iCE_SCK_A
iCE_SI_A
iCE_SO_A
CRSTb_A
SPARE_A0
SPARE_A1
SPARE_A2
proc_intr_A
CDONE
CDONE_A
CRSTb_A
CRSTb_A
SPARE_A2