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ECP5 and ECP5-5G Hi

g

h-Speed I/O Interface

Data Valid Module

The DQSBUF block generates a DATAVALID signal. This signal indicates the timing that the IDDR module drives 
the valid read data transmitting to the FPGA fabric. DATAVALID is a level-sensitive active high signal and indicates 
that the read data output from the IDDR module is valid while it is asserted high. The DATAVALID signal can stay 
asserted during the IDDR module outputs back-to-back valid read data until all consecutive read operations are 
completed. 

READ Pulse Positionin

g

 Optimization

The memory controller is required to provide the READ1/0 signal to the DQSBUF block to position the internal 
READ pulse and generate the DATAVALID output that indicates the proper timing window of the valid read data. 
The internal READ pulse is also used to get a clean internal DQS signal between the preamble and postamble 
periods. The clean DQS is 90° shifted internally to be used to capture the read data. 

Due to the DQS round trip delay that includes PCB routing and I/O pad delays, proper positioning of the READ 
pulse is crucial for successful read operations. The ECP5 and ECP5-5G device DQSBUF block provides the 
dynamic READ pulse positioning function which allows the memory controller to locate the READ pulse to an 
appropriate timing window for the read operations by monitoring the positioning result. 

The READCLKSEL2/1/0 and BURSTDET signals are used to accomplish the READ pulse positioning function for 
a corresponding DQSBUF block. The READ1/0, READCLKSEL2/1/0 signals are driven by the user logic and are 
part of the DDR memory controller.

The READ1/0 signal needs to be asserted high a certain amount of time before the read preamble starts. The sug-
gested READ1/0 signal assertion timing and the required duration of assertion are listed in Table 4. When the inter-
nal READ pulse is properly positioned, BURSTDET will be asserted high and guarantee that the generated 
DATAVALID signal properly indicates the valid read data time window. The READ1/0 signal must stay asserted as 
long as the number of SCLK cycles that is equal to one fourth of the total burst length as listed in the Table 4. 

Table 4. READ Training Signals and Initial Read Assertion Position

Once the memory controller initially positions the internal READ pulse using the READ1/0 and READCLKSEL2/1/0 
signals, BURSTDET can be used to monitor the positioning result to optimize the READ pulse position. The 
BURSTDET signal provides a feedback mechanism to inform the memory controller whether the READ pulse has 
reached to the optimal position for the read operations or not with the current READ1/0 and READCLKSEL2/1/0 
values. When it reaches to the optimal position, BURSTDET is asserted High after a read operation. Otherwise, 
BURSTDET will remain Low. A minimum burst length of eight on the memory bus must be used in the training pro-
cess. This can be done either with two consecutive BL4 (BL=4) read accesses or one BL8 read access. Any even 
number of BL4, or any multiplication of BL8(BL=8) can also be used. This read pulse training process must be per-
formed during the initial training and can also be periodically calibrated during the normal operations. 

The BURSTDET signal is asserted after the last DQS transition is completed during a read operation and lasts until 
the next read cycle is started. Once a read operation is started, the memory controller should wait until the DAT-
AVALID signal from DQSBUFM is asserted and then sample the BURSTDET signal at the next cycle to monitor the 
READ pulse positioning result. If there is no assertion on BURSTDET, it means that the READ pulse has not been 
located to the optimal position yet. Then, the memory controller needs to shift the READ1/0 signal and/or increase 
the READCLKSEL2/1/0 value until it detects a BURSTDET assertion. It is recommended that at least 128 read 

Gearin

g

 Mode

READ Control

DQSBUF Block

Initial READ Asser-

tion Position*

READ Width in 

SCLK

X2 Gearing 
(All DDR Memory Interfaces)

READ1
READ0
READCLKSEL2
READCLKSEL1
READCLKSEL0

DQSBUFM

At least 5.5T before 

preamble

Total Burst Length / 4

Note: Subject to change after validation tests. The number shown does not include DQS round trip delay.
1T = 1 tCK memory clock cycle

Содержание ECP5 Versa

Страница 1: ...discusses how to utilize the capabilities of the ECP5 and ECP5 5G devices to implement high speed generic DDR interface and the DDR memory interfaces Refer to the Implementing DDR Memory Interfaces se...

Страница 2: ...these edge clocks can be used to implement a high speed interface There is an Edge Clock Bridge ECLKBRIDGECS that will allow users to build large interfaces by bridg ing the edge clocks from one bank...

Страница 3: ...when interfacing to DDR memories It generates the delay on the DQS pin of the DQS lane to provide a 90o phase shift on DQS to clock the DDR data at the center The delay is set by a delay code generat...

Страница 4: ...t Similar to input interfaces the 2X gearing is used for data rate higher than 400Mbps which would require higher than 200 MHz system clock Here the ODDR element receives 4 bit wide data from the FPGA...

Страница 5: ...Aligned GDDRX1_RX SCLK Aligned DDR 1x Input using SCLK Data is edge to edge with incoming clock DLLDEL will be used to shift the incoming clock Receive DDRX1 Centered GDDRX1_RX SCLK Centered DDR x1 I...

Страница 6: ...eric 1X gearing Receive interface using SCLK The clock is coming in centered to the Data This inter face must be used for speeds below 200 MHz This DDR interface uses the following modules IDDRX1F ele...

Страница 7: ...YG and DELAYF element to indicate the interface type so that the cor rect delay value can be set in the delay element Dynamic Margin adjustment in the DDRDLLA module can be optionally used to adjust t...

Страница 8: ...y set The type of delay required can be selected through Clarity Designer DEL_MODE attribute is used with DELAYG and DELAYF element to indicate the interface type so that the cor rect delay value can...

Страница 9: ...t the incoming clock routed to the Edge clock ECLK clock tree through the ECLKSYNCB module CLKDIVF module is used to divide the incoming clock by 2 Static data delay element DELAYG to delay the incomi...

Страница 10: ...The Receiver Synchronization RX_SYNC soft IP is required for the aligned interfaces to prevent stability issues that may occur due to this loop at startup The soft IP will prevent any updates to the D...

Страница 11: ...en by a soft IP When in high speed mode The OHSOLS1 of the element is active The OHSOLS1 of the data IMIPI element is connected to the Data input GDDRX2_RX ECLK Centered Interface The OHSOLS1 of the c...

Страница 12: ...the Edge clock ECLK clock tree through the ECLKSYNCB module CLKDIVF module is used to divide the ECLK by 3 5 and is routed to the primary clock tree used as the SCLK input A second IDDRX71B element i...

Страница 13: ...ace uses the following modules ODDRX1F element is used to generate the data output The primary clock SCLK is used as the clock for both data and clock generation Optionally the user can choose to use...

Страница 14: ...rate the clock output is delayed 90 to center to data at the output Both these clocks are routed on primary clock tree Optionally the user can choose to use the DELAYG or DELAYF element to delay the o...

Страница 15: ...tionally the user can choose to use the DELAYG or DELAYF element to delay the data output The output data can be optionally tristated using either a Tristate input going through an I O register Figure...

Страница 16: ...ed to the SCLK net The user must set the timing preferences as per section Timing Analysis Requirement GDDRX71_TX ECLK This interface is used to implement transmit side of the 7 1 LVDS interface DDR u...

Страница 17: ...etails Receive Interface Guidelines Differential DDR interface can be implemented on the Left and Right sides of the device There are 4 different edge clocks available per side two per bank Each of th...

Страница 18: ...aring will use the primary clock resource You can use as many interfaces as the num ber of primary clocks supported in the device Clocking Guidelines for Generic DDR Interface The edge clock and prima...

Страница 19: ...or DLL DDR Input Setup and Hold Time Constraints All of the Receive RX interfaces both x1 and x2 can be constrained with setup and hold preference Receive Centered Interface Figure 19 below shows the...

Страница 20: ...CLKPORT clk Note Negative number is used for SETUP time as the data occurs after the clock edge in this case The External Switching Characteristics section of DS1044 ECP5 and ECP5 5G Family Data Sheet...

Страница 21: ...ax Timing Analysis Transmit Centered Interfaces In this case the transmit clock is expected to be centered to the data when leaving the device Figure 22 shows the timing for a centered transmit interf...

Страница 22: ...k Output Port clk Input Clock Port The values for tDVBCKGDDR and tDVACKGDDR can be picked up from the External Switching Characteristics section of DS1044 ECP5 and ECP5 5G Family Data Sheet for the MA...

Страница 23: ...e signal called DQS for high speed operation The DQS strobe is a differential signal except for DDR2 you can choose between single ended or differential DQS strobe Figure 24 shows typical DDR memory s...

Страница 24: ...eveling may be supported if user emulates the fly by rout ing using board traces You can see more information in the DDR pin placement and layout guidelines section of this document One major differen...

Страница 25: ...l LPDDR2 LPDDR3 Memory Interface Figure 26 DQ DQS During Read Figure 27 DQ DQS During Write DQS at PIN DQ at PIN DQS at IDDR DQ at IDDR 90 degree phase shift between DQS pin to IDDR Preamble Postamble...

Страница 26: ...multiplexed into a single outgoing DDR data stream Generate ADDR CMD signal edge aligned to CK falling edge to maximize the tIS and tIH timing parameters Differential CK signals CK and CK need to be g...

Страница 27: ...these DDR interface needs ECP5 and ECP5 5G devices support DQS signals on the left and right sides of the device Each DQS signal spans across 12 to 16 I Os Any 10 for DDR2 or 11 for DDR2 DDR3 LPDDR2...

Страница 28: ...de DDRDEL from the on chip DDRDLL The code generated by DDRDLL is connected to the DQSBUF circuit to perform 90 read phase shift and 90 write phase shift DDRDLL requires the frequency reference from P...

Страница 29: ...e READ1 0 signal must stay asserted as long as the number of SCLK cycles that is equal to one fourth of the total burst length as listed in the Table 4 Table 4 READ Training Signals and Initial Read A...

Страница 30: ...AD pulse needs to be moved to the next timing window Step 3 To shift the READ pulse timing window READ1 0 can be moved to the next cycle If a READ bit is asserted in the next cycle while the other REA...

Страница 31: ...e continuous ECLK The FIFO is written by the DQS strobe and read back by ECLK which has the identical frequency rate as DQS The input FIFO also performs the read leveling function When each DQS strobe...

Страница 32: ...e DQSBUFM module to the DQS clock tree The DQSBUFM receives the delay code from DDRDLLA and generates the delayed DQS signal to IDDRX2DQA DQSR90 D Q0 Q1 RST SCLK RDPNTR 2 0 WRPNTR 2 0 IDDRX2DQA DQSR90...

Страница 33: ...n without interrupting interface operation When a DDR memory interface IP is gen erated from Clarity Designer the MEM_SYNC soft IP block is also generated and included The Pause_sync output of the MEM...

Страница 34: ...ed inside the ODDRX2 module before data is transferred to the DQSW270 and DQSW clocks The ECLK is generated by the EHXPLLL module and the SCLK is generated by the CLKDIVF module both shown in the Read...

Страница 35: ...3 ODDRX2DQA module to generate the CA 9 0 outputs ODDRX2DQSB with D0 and D1 tied together and D2 and D3 tied together to generate CSN CKE signals ODDRX2DQSB with inputs tied to 0 and 1 is used to gene...

Страница 36: ...W270 D2 D3 SCLK ca n _in 0 ECLK DQSW Q PAUSE Pause_CA From Input side DDRDLLA CA 9 0 0 0 ca n _in 1 ca n _in 2 ca n _in 3 0 Pause output of MEM_SYNC Eclk from ECLKSYNCB as shown in the Input interface...

Страница 37: ...YNDELAY 7 0 PAUSE SCLK DQSW270 ECLK DQSW DQSR 90 WRPNTR 2 0 RDPNTR 2 0 DDR_reset Sclk from CLKDIVF as shown in the Input interface Eclk from ECLKSYNCB as shown in the Input interface D0 D1 SCLK RST Q...

Страница 38: ...side where another DDR memory interface is running at a differ ent frequency another available DDRDLLA for the side must be instantiated and used for the new interface The reference clock input to the...

Страница 39: ...Locate a 100 ohm resistor between the positive and negative clock signal OR Connect one end of an Rtt resistor to the positive pin and one end of another Rtt to the negative pin of a CK pair then conn...

Страница 40: ...ial SSTL type SSTL15D in DDR3 SSTL18D in DDR2 SSTL135D in DDR3L and HSUL12D in LPDDR2 LPDDR3 is selected Do not assign any signal to a DQS pad if used as differential strobe The software automatically...

Страница 41: ...or ground power source on the PCB Your design needs to drive the pseudo power I O pads according to the external connection i e you assign them as OUTPUT and let your design drive 1 for pseudo VCCIO...

Страница 42: ...hat includes all the DDR modules configured Planner Used to Plan the Placement of the various DDR Interfaces Figure 38 Clarity Design Main Window Note It is recommend that all the DDR modules required...

Страница 43: ...Clarity Designer Enter the name of the module Figure 39 shows the type of interface selected as SDR and module name entered This module can then be configured by clicking the Customize button Figure...

Страница 44: ...ce 1 256 16 Clock Frequency for this Interface Interface Speed 1 200 200 Bandwidth Calculated This is the calculated from the Clock frequency entered Calculated calculated Interface Interface selected...

Страница 45: ...ith the best interface selection The user can also if needed override the selection made for the interface in the Configuration Tab and customize the interface based on the design requirement FDEL for...

Страница 46: ...ulated with the selections Figure 43 shows the Configuration Tab for the selection made in Pre Configuration Tab GUI Option Range Interface Type Transmit Receive Receive MIPI I O Standard for this Int...

Страница 47: ...ers GUI Option Description Values Default Value Interface selection based on pre configuration Indicates interface is selected based on selection made in the Pre configuration tab Disabling this check...

Страница 48: ...nterfaces available for a given configuration Data Path Delay Data input can be optionally delayed using the DELAY block Default Value is selected based on Interface Type If Interface Type Receive Sta...

Страница 49: ...ays the achieved PLL output clock frequency Actual PLL output Fre quency achieved based on interface requirement CLKI Input Buffer Type The I O Standard for the PLL Ref erence Clock List of Legal Inpu...

Страница 50: ...rface Figure 44 GDDR_7 1 Option Selected in the Catalog Tab of Clarity Designer Clicking Customize displays the Configuration Tab where the 7 1 LVDS interface can be configured Figure 45 shows the Con...

Страница 51: ...ce select DDR_MEM option under Architecture Modules IO in the Catalog Tab of Clarity Designer Enter the name of the module Figure 46 shows the type of interface selected as GDDR_MEM and module name en...

Страница 52: ...52 ECP5 and ECP5 5G High Speed I O Interface Figure 46 DDR_MEM Option Selected in the Catalog Tab of Clarity Designer Figure 47 shows the Configuration Tab for the DDR_MEM interface...

Страница 53: ...or DDR pins DDR2 SSTL18_I STL18_II DDR3 SSTL15_I SSTL15_II DDR3L SSTL135_I SSTL135_II LPDDR2 HSUL12 LPDDR3 HSUL12 DDR2 SSTL18_I DDR3 SSTL15_I DDR3L SSTL135_I LPDDR2 HSUL2 LPDDR3 HSUL12 DDR Memory Freq...

Страница 54: ...DR2 DQS IO buffer type selection Single ended Differential Single ended Clock Address Com mand Clock address command pins added with this option checked ENABLED DISABLED DISABLED Data Mask Data mask p...

Страница 55: ...Command Parameters GUI Option Range Default Value Number of Clocks DDR2 1 2 4 DDR3 1 2 4 DDR3L 1 2 4 LPDDR2 1 LPDDR3 1 DDR3 1 DDR2 1 DDR3L 1 LPDDR2 1 LPDDR3 1 Address Width DDR2 13 16 DDR3 13 16 DDR3...

Страница 56: ...Table 13 shows the available values in this tab Number of Chip Selects DDR2 1 2 4 DDR3 1 2 4 DDR3L 1 2 4 LPDDR2 1 LPDDR3 1 DDR2 1 DDR3 1 DDR3L 1 LPDDR2 1 LPDDR3 1 Number of Clock Enables Number of Chi...

Страница 57: ...he selected location The planner takes into account all the clocking placement requirements any architecture limitations for each type DDR interface If any of the placement rules are violated the plan...

Страница 58: ...58 ECP5 and ECP5 5G High Speed I O Interface Figure 50 DDR Modules Paced Using Clarity Design Planner DDRDLL PLL ECLK tree CLKDIV DQS Group IO Logic...

Страница 59: ...alue for Zero Hold time delay based on Interface Type Fixed Delay values entered by the user The data input to this block can also be dynamically updated using counter up and down controls You can opt...

Страница 60: ...sing this module Figure 52 DELAYG Primitive Table 16 DELAYG Port List Port I O Description A I Data input from pin or output register block LOADN I 0 on LOADN will reset to default delay setting MOVE...

Страница 61: ...elements to delay the DQS input or in the DLLDEL module to delay the input clock DDRDLL by default will generate 90degree phase shift DDRDLLA Figure 53 DDRDLLA Primitive Attribute Description Values1...

Страница 62: ...ZE I Releases the DDRDLL input clock DDRDEL O The delay codes from the DDRDLL to be used in DQSBUF or DLLDEL LOCK O Lock output to indicate the DDRDLL has valid delay output DCNTL 7 0 O The delay code...

Страница 63: ...re the primitives used to implement various Generic DDR Input and Output data IDDRX1F This primitive is used to receive Generic DDR with 1X gearing Figure 55 IDDDRX1F Primitive Table 22 IDDRX1F Port L...

Страница 64: ...D I DDR data input ECLK I Fast edge clock SCLK I Primary clock input divide by 2 of ECLK RST I Reset to DDR registers ALIGNWD I This signal is used for word alignment It will shift the word by one bit...

Страница 65: ...Primitive Port I O Description D0 D1 I Parallel data input to ODDR D0 is sent out first then D1 SCLK I SCLK input RST I Reset input Q O DDR data output on both edges of SCLK Port I O Description D0 D...

Страница 66: ...flected in the delay DQS signal A soft IP is required to detect the code changes from the DDRDLL and update the MOVE pulse input to the DQSBUF so that the DDRDLL code changes can be tracked If margin...

Страница 67: ...RECTION I Indicates delay direction 1 decreases the delay count 0 increases the delay count Used to change delay on the read side DQS RDCFLAG O Indicates the delay counter has reached max value for th...

Страница 68: ...BUF DQS_LI_DEL_ADJ Sign bit for READ delay adjustment DDR input PLUS MINUS PLUS All DQS_LI_DEL_VA Value of delay for input DDR 0 to 255 PLUS 1 to 256 MINUS Note1 All DQS_LO_DEL_ADJ Sign bit for WRITE...

Страница 69: ...DQSR90 I DQS clock Input ECLK I Fast edge clock SCLK I Primary clock input divide by 2 of ECLK RDPNTR 2 0 I Read pointer from the DQSBUF module used to transfer data to ECLK WRPNTR 2 0 I Write pointe...

Страница 70: ...DR Primitives for DQS Output Following are the primitives used to implement the DQS outputs to the DDR memory ODDRX2DQSB This primitive is used to generate DQS clock output for DDR2 and DDR3 memory Fi...

Страница 71: ...tristate control for DQS output Figure 66 TSHX2DQSA Primitive Port I O Description D0 D1 D2 D3 I Data input to the ODDR D0 is output first D3 last ECLK I ECLK input SCLK I SCLK input DQSW I DQSW inclu...

Страница 72: ...y with x2 gearing and write leveling Figure 67 OSHX2A Primitive Table 37 OSHX2A Port List Port I O Description T0 T1 I Tristate input T0 is output first then T1 ECLK I ECLK input 2x speed of SCLK SCLK...

Страница 73: ...r Aligned Interfaces Yes GDDR_SYNC Needed to tolerate large skew between stop and reset input Yes MEM_SYNC Needed to avoid issues on DDR memory bus and update code in operation without interrupting in...

Страница 74: ...he RX_CLK or divided version It can be other low speed continuously running clock For example oscillator clock RST IN Active high reset to this sync circuit When RST 1 STOP 0 DDR_RESET 1 READY 0 START...

Страница 75: ...RESET OUT Reset to DDRDLL DDR_RESET OUT Reset to all IDDRX components and CLKDIV READY OUT Indicate that startup is finished and RX circuit is ready to operate Port In Out Descriptions START_CLK IN St...

Страница 76: ...es the 7 bit bus by 2 bits In maximum 7 ALIGNWD operations the word will loop through all 7 possibilities The goal is to get 7 b1100011 7 h63 in the clock word The clock word is the clock 4 bit 1 and...

Страница 77: ...LK IN Clock used to drive digital filter Min freq 100 MHz Recommendation is to use internal oscillator at 133 MHz LS IN Low speed signal from MIPI PHY RST IN Active high reset When RST 1 LSOUT 0 LS_OU...

Страница 78: ...2_RX ECLK Centered Interface Dynamic Data delay Figure 10 GDDRX2_RX ECLK Aligned Interface Static Delay Figure 11 GDDRX2_RX ECLK Aligned Interface Dynamic Data Clock Delay Figure 12 GDDRX2_RX MIPI Fig...

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