Lattice Semiconductor CertusPro-NX, Руководство по эксплуатации

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CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 61
All rights reserved. CONFIDENTIAL
P0 P1 D0 D1
bit[9:0]
D2 D3
P0
D2
D3
P3
D1
D0 D5
D4 D7
D6 D9
D8 P2
P1
Example 1: 10-bit bus, 2-byte Sync Code
D4
Pn
Dn
The location where the first byte of synchronization
code is expected to appear in subsequent input data
bit[9:0]
bit[19:10]
Example 2: 20-bit bus, 4-byte Sync Code
The first byte of detected synchronization code
Figure 6.18. The Expected Location of Synchronization Code
Tx Lane-to-lane Deskew
One clock cycle lane-to-lane skew may be introduced by the uncertain latency of Tx FIFO (works as phase
compensation FIFO). The Tx Lane-to-lane Deskew FIFO is implemented to eliminate this skew between two different Tx
channels by using the common clock from Quad Common module.
The common clock has no frequency difference with respect to each channel’s tx_pcs_clk, but can have a big phase
difference. The Quad Common module selects one channel’s tx_pcs_clk as the write clock of all channels’ Tx
Lane-to-Lane Deskew FIFO, while the read clock of each channel is the original tx_pcs_clk generated by each channel’s
PMA. Check the
MPCS Quad Clock Detail section for more details about this common clock.
The Tx Lane-to-lane Deskew FIFO can be disabled in single lane application or Tx FIFO is bypassed.
Elastic Buffer
This Elastic Buffer (or named as Clock Compensation Buffer in some documents) performs clock frequency adjustment
between the recovered receive clock domain and the local system clock domain. The Elastic Buffer performs clock
compensation by inserting or deleting bytes at the position where SKIP pattern is detected, without causing loss of
packet data. A 32-byte Elastic FIFO (CTC FIFO) is implemented to temporarily buffer coming data from recovered
receive clock domain and transfer the data to local system clock domain.
The Elastic Buffer can optionally be enabled or disabled. Figure 6.19 shows the format of common SKIP pattern used by
most 8B/10B PCS based protocols: one COM byte optionally followed by 1 to 3 SKP bytes.
COM
SKP0
SKP1
SKP2
Byte3
Byte2
Byte1
Byte0
Figure 6.19. SKIP Pattern Format
The length of SKIP pattern can be set to 1, 2, or 4 byte. In 1-byte length mode, only Byte 0 is used; in 2-byte length
mode, Byte 0 and Byte 1 are used, and Byte 0 holds the pattern byte received firstly (usually a COM byte).
This Elastic Buffer provides two SKIP patterns: primary and secondary. Primary SKIP pattern is always enabled, and
secondary SKIP pattern can optionally be enabled. This module matches either of these two SKIP patterns, if the
secondary SKIP pattern is enabled. However, only primary SKIP pattern can be used in 8-bit data mode.
A mask code is provided to allow partially matching the SKIP pattern. Refer to Figure 6.20. The mask code has 4-bit
length, each bit corresponds to one byte of the SKIP pattern. Value 1 means the corresponding byte is masked, and
value 0 means not masked. SKIP byte being masked is ignored during SKIP matching. It is important to note that the
mask code is applicable for both primary and secondary SKIP patterns.