
ML7406 Family LSIs Hardware Design Manual
FEXL7406DG-01
15
10. Application circuit
[Note]
·These component values are the reference value. LAPIS Semiconductor does not guarantee the values.
·The XIN (#5) pin should be OPEN when using TCXO or SPXO.
ML7406
LP
(26)
PA_OUT(20)
LNA_P(24)
IND2
(30)
Back side is GND pad
VDDIO(9)
GND_VCO
(29)
Digital
I/O
A_MON(23)
SMA2(ANT2)
SMA1(ANT1)
IC5
μPG2164T5N
1
SDI(15)
SDO(12)
SCLK(13)
SCEN(14)
GPIO0(16)
EXT_CLK(10)
RESETN(8)
GPIO1(17)
GPIO2(18)
GPIO3(19)
REGPDIN(11)
C33
1000pF
C34
0.1uF
C27
1000pF
C25
0.1uF
C24
1000pF
C42
C41
C40
1000pF
C51
1000pF
L2
L3
C45
L6
L5
C47
C48
L1
C5
C22
1000pF
C18
1000pF
C16
1000pF
C14
1000pF
C15
0.1uF
R3
C3
C2
X1
26MHz
C21
0.1uF
C44
GND
R1
75kΩ
VDD_PA(22)
REG_PA(21)
C1
C29
100pF
C30
0.01uF
C36
0.1uF
C35
1000pF
C38
100pF
C37
1uF
N.C.
(7)
R1 is necessary
for temperature
meter
4
6
5
2
3
C4
VDD_RF
(25)
VB_EXT
(31)
VDD_VCO
(32)
REG_OUT
(3)
VBG
(2)
REG_CORE
(4)
VDD_CP
(27)
VDD_REG(1)
IND1
(28)
XIN
(5)
XOUT
(6)
C52
1000pF
C39
1000pF
TCXO/
SPXO
C6
IC2
About the peripheral parts of pin #5 and
#6, please refer the section 2.