
3: Open-Q 865XR SOM Development Kit
Open-Q 865XR SOM Development Kit User Guide
32
PCIe USB Enable DIP Switch (6). If the DIP switch is closed, the USB 3.1 Type A connector
J2300 (5) is not functional.
•
Pin 25 of the M.2 Socket connects to GPIO_117. GPIO_117 is shared with general purpose user
button (see section 3.7.7). Concurrent usage of both the user button and M.2 socket may not be
possible.
3.7.17
Digital IO Expansion Header J2100 (23)
The Open-Q 865XR SOM Development Kit includes a digital IO expansion header J2100 which provides
access to a selection of SOM GPIO signals and power rails. See item 23 in Figure 1 for the carrier board
location of this header. The pinout for this header is shown in the table below.
Table 13. Digital IO Expansion Header J2100 Pinout
Pin
No
Signal
Description
Pin
No
Signal
Description
1
No Net
No Net
2
VREG_S4A_1P8
SOM LDO Regulator S4A
+1.8V
3
GPIO_41_QUP14_FP_S
PI_MOSI
CPU
GPIO41/QUP1
4
4
MB_VREG_3P3
Carrier board switching
regulator. 3.3V
5
GPIO_40_QUP14_FP_S
PI_MISO
CPU
GPIO40/QUP1
4
6
PM8150L_GP10_PWM
PM8150L GPIO10
7
GPIO_43_QUP14_FP_S
PI_CS
CPU
GPIO43/QUP1
4
8
GPIO_9_QUP4_CAM_S
PI1_MOSI
CPU GPIO9/QUP4
9
GPIO_42_QUP14_FP_S
PI_CLK
CPU
GPIO42/QUP1
4
10
GPIO_8_QUP4_CAM_S
PI1_MISO
CPU GPIO8/QUP4
11
No Net
No Net
12
GPIO_11_QUP4_CAM_
SPI1_CS0_N
CPU GPIO11/QUP4
13
GPIO_57_QUP18_SPI_
MOSI
CPU
GPIO57/QUP1
8
14
GPIO_10_QUP4_CAM_
SPI1_CLK
CPU GPIO10/QUP4
15
GPIO_56_QUP18_SPI_
MISO
CPU
GPIO56/QUP1
8
16
GPIO_59_QUP18_SPI_
CS_N
CPU GPIO59/QUP18
17
GND
System
Ground
18
GPIO_58_QUP18_SPI_
CLK
CPU GPIO58/QUP18