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The device and principle of operation L-502.
3.3.4.1. Restrictions on the current implementation of asynchronous output during
external synchronization.
Asynchronous output to digital lines and to DAC in the operating mode will always work
when configured for internal synchronization. But asynchronous output to digital lines and to the
DAC will not function in the standby mode for external synchronization of the start of data
acquisition or waiti
ng for more than 1 μs of the external clock of the ADC conversion.
3.3.5. General principle for synchronization in L-502.
A simplified block diagram is presented on
to explain the general arrangement of the
synchronization system in L-502. L-502 synchronization system consists of two parts: primary and
secondary synchronization circuits.
3.3.5.1. Primary synchronization.
The primary synchronization circuit (
I
)
according to the settings selects the corresponding
external or internal source of the reference frequency, as well as the external or internal source of
the start signal. Using the selected signals, circuit
I
generates an internal reference signal
f
ref
as a
sequence of synchronization pulses with a period
t
ref
. Moreover, the beginning of this sequence is
strictly bound by this scheme to the external or internal
start event
, and all I/O equipment is
synchronized (and simultaneously starts) from this sequence: nodes of the ADC (including the logic
of the control table), DAC and digital I/O. These nodes contain the corresponding frequency
dividers
f
ref
.
We list all possible options for user settings related to the
selection of sources of reference
frequency signals
:
•
The internal generator 2.0/1.5 MHz of this module L-502 (the "default" setting)
•
The reference frequency from the DI_SYN1 input (on the front or on the drop)
•
The reference frequency from the DI_SYN2 input (on the front or on the drop)
•
The reference frequency is from the CONV_IN input from the neighboring L-502, which acts as the
master.
We list all possible options for user settings for
selecting sources of the start event of the
L-502
I/O system:
•
Program start from PC (default setting)
•
On the signal from the input DI_SYN1 (on the front or on the drop)
•
On the signal from the input DI_SYN2 (on the front or on the drop)
•
By the signal from the input START_IN from the neighboring L-502, which acts as the master.
Each L-502 module always translates via its CONV_OUT and START_OUT outputs,
respectively, its internal reference and start signals for one L-502 slave module, if it is connected to
these outputs via a
synchronization cable
and is located in the neighboring PCIe slot of the PC
system unit.
The L-502 module can simultaneously be the master for the neighboring L-502 located on one
side of this PCI-E slot and slave for the other neighboring L-502 on the opposite side. Thus,
synchronization of several L-502, connected by a chain, is supported in an amount limited by the
number of PCI-E-s of one PC motherboard.
The primary synchronization circuit provides synchronization of the frequency and phase of
the ADC, DAC and cycle cycles of the digital input and output system. It is understood that in a
