Kvaser PCIEcan User's Guide
11(17)
Kvaser AB, Mölndal, Sweden
— www.kvaser.com
6.4 Interrupts
The PCIEcan uses one PCI Express bus interrupt, INTA#. It is asserted whenever one or
more SJA1000’s have their interrupts active. To reset an active interrupt, read the interrupt
status register in all present SJA1000s
– the interrupt of the corresponding SJA1000 will then
automatically clear.
To check the status of the interrupt line, test the INTERRUPT ASSERTED bit (number 23) in
the INTCSR register in the
“S5920”.
To enable or disable interrupts from the PCIEcan, use the ADD-ON INTERRUPT PIN
ENABLE (bit 13) in the INTCSR register in the
“S5920”.
6.5 Registers in the Xilinx
The Xilinx FPGA implements a few registers.
Address offset
Register
Usage
0
– 6
Reserved, do not use
7
VERINT
Bit 7 - 4 contains the revision number of the
FPGA configuration. 15 is the first revision, 14 is
the next, and so on.
The current FPGA revision number is 10 (which is read from the VERINT register as
1110xxxx). Future revisions (9, 8, 7, …) will remain compatible with revision 10.
6.6 PCI Configuration Data
The following data are configured automatically into the Xilinx FPGA PCI controller when
power is applied to the card.
Item
Value
Vendor Id
0x1A07
Device Id
0x0008
Revision Id
00
Class Code
0xffff00 (means: no base class code defined for
device)
Subsystem Vendor Id
0x1A07
Subsystem Device Id
0x0008
