Kurzweil CUP2, Руководство по обслуживанию

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General
The Engine PCB contains the system CPU (a 200MHZ Renesas SH2A integrated
microcontroller), sound synthesis ASIC (Kurzweil MARA), and player control/user interface
scanning. The following paragraphs give a brief summary of these major functions and
associated functional blocks.
Boot Sequence
The CUP2 uses a modern tiered memory architecture and boots much like a desktop computer.
The sequence is essentially:
1. The Interface PCB, which contains the power supply, produces a signal (PWRUPRST_L)
that goes high when the main DC power (+5V) has been stable for approximately 0.5
seconds.
2. The CPU (U1) is enabled and begins fetching instructions from Boot Flash (U4), which
contains the initial bootup code.
3. After initialization, the bootup code checks the contents of the NAND Flash, U3. U3 is
essentially a solid-state disk drive that acts like the hard disk in a desktop computer. If it is
formatted and has the necessary
 les installed, the ““second level”” boot loader program is
read into RAM (U2) and run. Otherwise a more limited function boot loader program, also
in the Boot Flash (U4), is run. (Normally the latter should only happen at the factory before
installing the OS for the
 rst time.)
4. The second level boot loader then loads the operating system software and soundware
““object data”” from U3. The dot matrix display will show a series of line patterns during
this time.
5. Bootup is now complete and the unit is ready to play.
Note: Step 4 is aborted if the Play/Stop button is held down during bootup. The boot loader
can then be used to update the operating system software and soundware objects or run the
diagnostics.
CPU
The CPU (U1, page 1, zone C4) is a Renesas SH7023, which is a member of the SH-2A family.
This highly ef
 cient, low-power, RISC processor is very effective in musical instruments.
X1 is the CPU clock crystal that operates at 16.67MHz. The CPU multiplies that by four to
produce the 66.67MHz Bus Clock (called SDRAM_CLK, U1-50) and by 12 to make the 200MHz
core clock.
Reset to the CPU (U1-59) comes from the reset circuit on page 5, zone A4. This circuit receives
Power OK from the Interface PCB via J23.
Printed Circuit Boards
Engine PCB
2- 2