QSEVEN-Q7AL - Rev.1.0
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The BIOS does not support being split between two chips. Booting takes place either from
the module SPI or from the baseboard SPI.
The following table lists the supported SPI Boot Flash types for the 8-SOIC package.
Table 5: Supported SPI Boot Flash Types for 8-SOIC Package
Size
Manufacturer
Part Number
Device ID
16MB
Maxim
MX25L12835F
0x20
16MB
Winbond
W25Q128
0x90
16MB
Micron
N25Q128A
0xBA
Fast I2C
5.4.
Fast I2C supports transfer between components on the same board. The Qseven-Q7AL features an embedded I2C
controller connected to the LPC Bus.
The I2C controller supports:
Multimaster transfers
Clock stretching
Collision detection
Interruption on completion of an operation
UART
5.5.
The UART implements a serial communication interface and supports to serial RX/TX port defined in the QSEVEN®
specification on pin 171 (UART0_TX) and pin A 177 (UART0_RX) for UART0. The UART controller is fully 16550A
compatible.
UART features are:
On-Chip bit rate (baud rate) generator
With handshake lines
Interrupt function to the host
FIFO buffer for incoming and outgoing data
Dual Staged Watchdog Timer (WTD)
5.6.
A watchdog timer (WDT) or (computer operating properly (COP) timer) is a computer hardware or software timer. If
there is a fault condition in the main program, the watchdog triggers a system reset or other corrective actions. The
intention is to bring the system back from the non-responsive state to normal operation.
Possible fault conditions are a hang, or neglecting to service the watchdog regularly. Such as writing a “service pulse”
to it, also referred to as “kicking the dog”, “petting the dog”, “feeding the watchdog” or “triggering the watchdog”.
The Qseven-Q7AL offers a watchdog that works with two stages that can be programmed independently and used
stage by stage.