Software Setups
3-19
Time-out
The programmable watchdog has two stages: the first stage has a variable time-out while
the second stage has a fixed one.
The first stage time-out is chosen at runtime from eight preset values (see table below). The
first stage time-out generates an NMI interrupt (if enabled in register n96h, bit 7). An
appropriate NMI handler must be written, otherwise this will be treated as a parity error by
the default BIOS NMI handler; see register n96h description for a suggestion on how to do
this.
The second stage times-out 8.6ms
±
10% (depending on the temperature) after the first one
and generates a master reset.
WDD[2..0]
NMI(T)
RESET(T)
000
16T
NMI(T)+8T
001
64T
NMI(T)+8T
010
256T
NMI(T)+8T
011
1024T
NMI(T)+8T
100
4096T
NMI(T)+8T
101
16384T
NMI(T)+8T
110
65536T
NMI(T)+8T
111
262144T
NMI(T)+8T
Time-out selection with T = 1.08ms (TBC)
A reset from the programmable watchdog is latched for reset source identification; see
reset history description in Section 4.3.
3.5.6. Thermal Management
The thermal management is built around two digital temperature sensors and a thermal
watchdog. Both devices can be programmed to set their outputs when the temperature of
the processor or the ambient temperature exceeds a programmable high limit, and reset its
output when the temperature is under a programmable low limit. A special routine is
implemented to throttle the CPU clock until the temperature falls below the programmed
low limit.
Please refer to Section 4.1.10
CPU/Board Features Setup– Thermal Management Options
for a complete information on thermal management setups.
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