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RI7SM User’s Manual 47
SDRAM RAS-to-CAS Delay
You can select RAS to CAS Delay time in HCLKs of 2/2 or 3/3. The system
board designer should set the values in this field, depending on the
DRAM installed. Do not change the values in this field unless you change
specifications of the installed DRAM or the installed CPU. The choices
are
2 and 3 .
SDRAM RAS Precharge Time
This option defines the length of time for Row Address Strobe is allowed
to precharge. The choices are
2 and 3 .
System BIOS Cacheable
The setting of Enabled allows caching of the system BIOS ROM at
F000h-FFFFFh, resulting in better system performance. However, if any
program writes to this memory area, a system error may result.
Video BIOS Cacheable
The Setting Enabled allows caching of the video BIOS ROM at
C0000h-F7FFFh, resulting in better video performance. However, if any
program writes to this memory area, a system error may result.
Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be reserved
for ISA boards. This memory must be mapped into the memory space below
16 MB. The choices are
Enabled and Disabled .
CPU Latency Timer
This field enable or disable the CPU latency timer. The default setting is
Enabled .
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select
Enabled to support compliance with PCI
specification version 2.1.
AGP Graphics Aperture Size
The field sets aperture size of the graphics. The aperture is a portion of the
PCI memory address range dedicated for graphics memory address space.
Host cycles that hit the aperture range are forwarded to the AGP without
any translation. The options available are 4M, 8M, 16M, 32M, 64M, 128M
and 256M. The default setting is
64M .