Introduction
CP6012
Page 1 - 12
ID 33274, Rev. 5.0
P R E L I M I N A R Y
Chi
pset
Intel® E7520
Intel® E7520 Memory Controller Hub:
•
Support for a single Intel® Core™ Duo or Intel® Core™2 Duo micropro-
cessor
•
64-bit AGTL/AGTL+ based System Bus interface up to 667 MHz
•
System Memory interface with optimized support for dual-channel, reg-
istered DDR2 SDRAM memory at 400 MHz with ECC
•
Two x4 PCI Express ports for Gigabit Ethernet interface
•
One x8 PCI Express port for XMC interface
•
RASUM (Reliability, Availability, Serviceability, Usability, and
Manageability) features:
•
Memory error detection and reporting of 1- and 2-bit errors including
correction of 1-bit failures
•
Integrated Memory Scrub Engine, which logs any uncorrectable
memory errors
•
Support for automatic read retry on uncorrectable errors
Intel® 6300ESB
Intel® 6300ESB I/O Controller Hub:
•
Dual channel SATA 150 interface
•
Integrated IDE controller Ultra ATA/100/66/33
•
USB host interface with up to four USB 1.1 or USB 2.0 ports
•
Firmware Hub interface support
•
Low pin count interface
•
PCI Rev. 2.2 compliant with support for 64-bit/66 MHz PCI operations
•
PCI Rev. 2.2 compliant with support for 32-bit/33 MHz PCI operations
•
Power management logic support
•
Enhanced DMA controller, interrupt controller, and timer functions
•
System Management Bus (SMBus) compatible with most I²C™
devices
•
Hub interface for the E7520 MCH
•
RTC controller
Table 1-2: CP6012 Main Specifications (Continued)
CP6012
SPECIFICATIONS
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