Koheron Alpha250, Руководство пользователя

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Description Offset Range
Identi cations 0x000 0x100
Precision DAC 0x100 0x100
RF ADC channel 0 0x200 0x100
RF ADC channel 1 0x300 0x100
Clock generator 0x400 0x100
RF DAC channel 0 0x500 0x100
RF DAC channel 1 0x600 0x100
Precision ADC 0x700 0x100
User application 0x1000 0x100
EEPROM map addressing.
Zynq I/Os
The Zynq XC7Z020-2CLG400I has 2 I/O banks for the programmable logic (Banks 34 and 35) with 48 IOs each. One bank (Bank 0) is
dedicated to the processing system with a multiplexed I/O (MIO) interface. The set of peripherals and interface buses is depicted
below.
Zynq peripherals and communication buses.
I/O constraints are de ned in the ports.xdc le (https://github.com/Koheron/koheron-
sdk/blob/master/boards/alpha250/con g/ports.xdc).