TK-7108
27
PLL Frequency Synthesizer
The PLL circuit generates the first local oscillator signal for
reception and the RF signal for transmission.
■
PLL
The frequency step of the PLL circuit is 5 or 6.25kHz. A
16.8MHz reference oscillator signal is divided at IC401 by a
fixed counter to produce the 5 or 6.25kHz reference fre-
quency. The voltage controlled oscillator (VCO) output signal
is buffer amplified by Q410, then divided in IC401 by a dual-
module programmable counter. The divided signal is com-
pared in phase with the 5 or 6.25kHz reference signal in the
phase comparator in IC401. The output signal from the
phase comparator is filtered through a low-pass filter and
passed to the VCO to control the oscillator frequency. (See
Fig. 6)
■
VCO
The operating frequency is generated by Q406 in transmit
mode and Q405 in receive mode. The oscillator frequency is
controlled by applying the VCO control voltage, obtained
from the phase comparator, to the varactor diodes (D405 and
D406 in transmit mode and D403 and D404 in receive mode).
The TX/RX pin is set low in receive mode causing Q408 and
Q407 to turn Q406 off, and turn Q405 on. The TX/RX pin is
set high in transmit mode. The outputs from Q405 and Q406
are amplified by Q410 and sent to the RF amplifiers.
■
Unlock Circuit
During reception, the 8RC signal goes high, the 8TC signal
goes low, and Q34 turns on. Q33 turns on and a voltage is
applied to the collector (8R). During transmission, the 8RC
signal goes low, the 8TC signal goes high and Q36 turns on.
Q35 turns on and a voltage is applied to 8T.
The CPU in the control unit monitors the PLL (IC401) LD
signal directly. When the PLL is unlocked during transmis-
sion, the PLL LD signal goes low. The CPU detects this sig-
nal and makes the 8TC signal low. When the 8TC signal goes
low, no voltage is applied to 8T, and no signal is transmitted.
D405,406
Q406
TX VCO
Q410
BUFF
AMP
D403,404
Q405
RX VCO
Q407,408
T/R SW
Charge
pump
LPF
Phase
comparator
1/M
1/N
5kHz/6.25kHz
5kHz/6.25kHz
REF
OSC
16.8MHz
PLL
DATA
IC401 : PLL IC
Q404
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Fig. 6
PLL circuit /
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IC101
CPU
Q34
SW
Q33
SW
IC401
PLL
Q36
SW
Q35
SW
LD
8RC
8C
8R
8T
8TC
PLL lock
: LD “H”
Fig. 7
Unlock circuit /
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